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    <title>topic While Loc is diligently in Software Archive</title>
    <link>https://community.intel.com/t5/Software-Archive/mic0-reset-failed/m-p/1017208#M36653</link>
    <description>&lt;P&gt;While Loc is diligently working to get an Ubuntu system up in our group's lab, I took a look at your micdebug file. The POST codes from the coprocessor (in host_dmesg.txt) end with F2 which, according to the chart in the MPSS user's guide, means that the GDDR memory training on the coprocessor failed.&lt;/P&gt;

&lt;P&gt;I also compared your full_lspci.txt against a machine I have access to and saw some things that don't look right to me. For example, in the section for the coprocessor, your output says:&lt;/P&gt;

&lt;P&gt;Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- &lt;STRONG&gt;ParErr-&lt;/STRONG&gt; Stepping- SERR- FastB2B- DisINTx+&lt;/P&gt;

&lt;P&gt;but I have&lt;/P&gt;

&lt;P&gt;Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- &lt;STRONG&gt;ParErr+&lt;/STRONG&gt; Stepping- SERR- FastB2B- DisINTx+&lt;/P&gt;

&lt;P&gt;There are a few other differences like that in the lspci entry for the coprocessor. Curious - and not in a good way.&lt;/P&gt;</description>
    <pubDate>Tue, 24 Feb 2015 11:19:17 GMT</pubDate>
    <dc:creator>Frances_R_Intel</dc:creator>
    <dc:date>2015-02-24T11:19:17Z</dc:date>
    <item>
      <title>mic0 reset failed</title>
      <link>https://community.intel.com/t5/Software-Archive/mic0-reset-failed/m-p/1017205#M36650</link>
      <description>&lt;P&gt;Hello!&lt;/P&gt;

&lt;P&gt;I am trying to make coprocessors work on Ubuntu 14.04 but I got stuck with error: mic0 reset failed. I have tried several methods noted in this form but I was not able to make it work. So, I am seeking help to make my mic work. Please, find my micbug as attachment.&lt;/P&gt;

&lt;P&gt;Thank you.&lt;/P&gt;

&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Sat, 21 Feb 2015 15:14:06 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Archive/mic0-reset-failed/m-p/1017205#M36650</guid>
      <dc:creator>Riazuddin_K_</dc:creator>
      <dc:date>2015-02-21T15:14:06Z</dc:date>
    </item>
    <item>
      <title>Hello Riazuddin, </title>
      <link>https://community.intel.com/t5/Software-Archive/mic0-reset-failed/m-p/1017206#M36651</link>
      <description>&lt;P&gt;Hello Riazuddin,&amp;nbsp;&lt;/P&gt;

&lt;P&gt;Can you please let us know which specific forum posts you followed? We are in process to get the system prepared with Ubuntu and Intel® MPSS and will be able to update you shortly with the correct recipe.&lt;/P&gt;

&lt;P&gt;Thank you for your patience.&lt;SPAN style="font-size: 1em; line-height: 1.5;"&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Mon, 23 Feb 2015 18:09:50 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Archive/mic0-reset-failed/m-p/1017206#M36651</guid>
      <dc:creator>Sunny_G_Intel</dc:creator>
      <dc:date>2015-02-23T18:09:50Z</dc:date>
    </item>
    <item>
      <title>Hello Sunny,</title>
      <link>https://community.intel.com/t5/Software-Archive/mic0-reset-failed/m-p/1017207#M36652</link>
      <description>&lt;P&gt;&lt;SPAN style="font-size: 1em; line-height: 1.5;"&gt;Hello Sunny,&lt;/SPAN&gt;&lt;/P&gt;

&lt;P&gt;&lt;SPAN style="font-size: 1em; line-height: 1.5;"&gt;Thank you very much for your reply; I really&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN style="font-size: 1em; line-height: 1.5;"&gt;appreciate&lt;/SPAN&gt;&lt;SPAN style="font-size: 1em; line-height: 1.5;"&gt;&amp;nbsp;your effort. I have read several forum articles but at the end, this is what i have done&lt;/SPAN&gt;&lt;SPAN style="font-size: 1em; line-height: 1.5;"&gt;:&lt;/SPAN&gt;&lt;/P&gt;

&lt;P&gt;&lt;A href="https://github.com/neel9102/michack/blob/master/michack_ubuntu_14.04_mpss_4_3.sh" target="_blank"&gt;https://github.com/neel9102/michack/blob/master/michack_ubuntu_14.04_mpss_4_3.sh&lt;/A&gt;&lt;/P&gt;

&lt;P&gt;Hope that helps. Thank you&lt;/P&gt;</description>
      <pubDate>Mon, 23 Feb 2015 19:15:00 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Archive/mic0-reset-failed/m-p/1017207#M36652</guid>
      <dc:creator>Riazuddin_K_</dc:creator>
      <dc:date>2015-02-23T19:15:00Z</dc:date>
    </item>
    <item>
      <title>While Loc is diligently</title>
      <link>https://community.intel.com/t5/Software-Archive/mic0-reset-failed/m-p/1017208#M36653</link>
      <description>&lt;P&gt;While Loc is diligently working to get an Ubuntu system up in our group's lab, I took a look at your micdebug file. The POST codes from the coprocessor (in host_dmesg.txt) end with F2 which, according to the chart in the MPSS user's guide, means that the GDDR memory training on the coprocessor failed.&lt;/P&gt;

&lt;P&gt;I also compared your full_lspci.txt against a machine I have access to and saw some things that don't look right to me. For example, in the section for the coprocessor, your output says:&lt;/P&gt;

&lt;P&gt;Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- &lt;STRONG&gt;ParErr-&lt;/STRONG&gt; Stepping- SERR- FastB2B- DisINTx+&lt;/P&gt;

&lt;P&gt;but I have&lt;/P&gt;

&lt;P&gt;Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- &lt;STRONG&gt;ParErr+&lt;/STRONG&gt; Stepping- SERR- FastB2B- DisINTx+&lt;/P&gt;

&lt;P&gt;There are a few other differences like that in the lspci entry for the coprocessor. Curious - and not in a good way.&lt;/P&gt;</description>
      <pubDate>Tue, 24 Feb 2015 11:19:17 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Archive/mic0-reset-failed/m-p/1017208#M36653</guid>
      <dc:creator>Frances_R_Intel</dc:creator>
      <dc:date>2015-02-24T11:19:17Z</dc:date>
    </item>
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