<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Recap of latest info:   in Software Archive</title>
    <link>https://community.intel.com/t5/Software-Archive/error-code-0xc0001c41/m-p/1020122#M37842</link>
    <description>&lt;P&gt;Recap of latest info: &amp;nbsp;&lt;BR /&gt;
	&amp;nbsp;-&amp;nbsp; CORRECTION: This was later corrected to AXXTPMe3 #&lt;SPAN style="font: 12.22px/20px Arial, 宋体, Tahoma, Helvetica, sans-serif; color: rgb(83, 87, 94); text-transform: none; text-indent: 0px; letter-spacing: normal; word-spacing: 0px; float: none; display: inline !important; white-space: normal; font-size-adjust: none; font-stretch: normal; background-color: rgb(255, 255, 255); -webkit-text-stroke-width: 0px;"&gt;922115, not 912429)&lt;/SPAN&gt;&lt;BR /&gt;
	&lt;SPAN style="font-family: Consolas, &amp;quot;Lucida Console&amp;quot;, Menlo, Monaco, &amp;quot;DejaVu Sans Mono&amp;quot;, monospace, sans-serif;"&gt;- if there's any chance that an 'earlier than 67 bin' was ever used, you need to run the revocation tool to remove earlier version (RACM at &lt;/SPAN&gt;&lt;A href="https://software.intel.com/protected-download/267276/183305"&gt;https://software.intel.com/protected-download/267276/183305&lt;/A&gt;&lt;SPAN style="font-family: Consolas, &amp;quot;Lucida Console&amp;quot;, Menlo, Monaco, &amp;quot;DejaVu Sans Mono&amp;quot;, monospace, sans-serif;"&gt;) and bring up to post 67 version.(as in BIOS 02.01.0002/4&lt;/SPAN&gt;&lt;BR /&gt;
	&lt;SPAN style="line-height: 1.5; font-size: 1em;"&gt;&amp;nbsp;- Use Bios&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN style="line-height: 1.5; font-family: Consolas, &amp;quot;Lucida Console&amp;quot;, Menlo, Monaco, &amp;quot;DejaVu Sans Mono&amp;quot;, monospace, sans-serif; font-size: 1em;"&gt;02.01.0004, but be sure you had loaded&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN style="line-height: 1.5; font-family: Consolas, &amp;quot;Lucida Console&amp;quot;, Menlo, Monaco, &amp;quot;DejaVu Sans Mono&amp;quot;, monospace, sans-serif; font-size: 1em;"&gt;02.01.0002 before loading 0004.&amp;nbsp;&lt;/SPAN&gt;&lt;BR /&gt;
	&lt;SPAN style="line-height: 1.5; font-family: Consolas, &amp;quot;Lucida Console&amp;quot;, Menlo, Monaco, &amp;quot;DejaVu Sans Mono&amp;quot;, monospace, sans-serif; font-size: 1em;"&gt;- try reprovisioning&lt;BR /&gt;
	- the 4th gen i5/i7 error codes are the ones to use.&amp;nbsp;&lt;BR /&gt;
	Please attach log if you still receive the&amp;nbsp;&lt;/SPAN&gt;0xc0001c41&amp;nbsp;(or any other) error.&lt;/P&gt;

&lt;P&gt;Also - please let us know if you ever had this S1200 TPM/TXT running without error.&lt;/P&gt;

&lt;P&gt;&lt;BR /&gt;
	&amp;nbsp;&lt;/P&gt;

&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
    <pubDate>Fri, 04 Jul 2014 06:27:00 GMT</pubDate>
    <dc:creator>Colleen_C_Intel</dc:creator>
    <dc:date>2014-07-04T06:27:00Z</dc:date>
    <item>
      <title>error code 0xc0001c41</title>
      <link>https://community.intel.com/t5/Software-Archive/error-code-0xc0001c41/m-p/1020118#M37838</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;

&lt;P&gt;I'm getting txt error code 0xc0001c41 with rebooting the system afterwards.&lt;/P&gt;

&lt;P&gt;I did the setup according to various material i studied on the web.&lt;BR /&gt;
	I also already had some chats within the tboot forum, w/o any progress.&lt;BR /&gt;
	Seems there's a similar setup (mentioned in the mailing list) with the same issue.&lt;BR /&gt;
	I guess there's a chance issue is not related to my setup&lt;/P&gt;

&lt;P&gt;According to SINIT_Errors.pdf error indicates "Invalid TPM NV index"&lt;BR /&gt;
	Guess the error is raise from within SINIT.&lt;/P&gt;

&lt;P&gt;Thanks for your suggestion in advance,&lt;BR /&gt;
	Dieter&lt;/P&gt;

&lt;P&gt;&amp;nbsp;&lt;/P&gt;

&lt;P&gt;Mainboard - Intel S1200RPL&lt;/P&gt;

&lt;P&gt;CPU - XEON E3-1265L&lt;BR /&gt;
	TPM - AXXTPME5&lt;BR /&gt;
	Boot - BIOS (i.e. no EFI, EFI boot shows identical behavior)&lt;BR /&gt;
	Distribution - Ubuntu 14.04 w/ tboot 1.8 (same w/ pretty new tboot 1.8.1)&lt;BR /&gt;
	SINIT - 4th_gen_i5_i7_SINIT_75.BIN (same w/ BIOS buildin SINIT)&lt;BR /&gt;
	&lt;BR /&gt;
	Attached below how the TPM is set up and the tboot dump.&lt;/P&gt;

&lt;P&gt;+ tpm_takeownership -z&lt;BR /&gt;
	Enter owner password:&lt;BR /&gt;
	Confirm password:&lt;BR /&gt;
	+ tpmnv_defindex -i 0x20000002 -s 8 -pv 0 -rl 0x07 -wl 0x07 -p password&lt;BR /&gt;
	Tspi_NV_DefineSpace failed failed: NVRAM area already exists (0x08313b)&lt;BR /&gt;
	&lt;BR /&gt;
	Command DefIndex failed:&lt;BR /&gt;
	TSS API failed&lt;BR /&gt;
	+ tpmnv_defindex -i owner -s 0x36 -p password&lt;BR /&gt;
	Haven't input permission value, use default value 0x2&lt;BR /&gt;
	&lt;BR /&gt;
	Successfully defined index 0x40000001 as permission 0x2, data size is 54&lt;BR /&gt;
	+ tpmnv_defindex -i 0x20000001 -s 512 -pv 0x02 -p password&lt;BR /&gt;
	&lt;BR /&gt;
	Successfully defined index 0x20000001 as permission 0x2, data size is 512&lt;BR /&gt;
	+ rm -r tmp&lt;BR /&gt;
	+ mkdir tmp&lt;BR /&gt;
	+ cd tmp&lt;BR /&gt;
	+ lcp_mlehash -c logging=serial,vga,memory /boot/tboot.gz lcp_crtpolelt&lt;BR /&gt;
	+ --create --type mle --ctrl 0x00 --minver 0 --out tboot_mle.elt&lt;BR /&gt;
	+ tboot_hash lcp_crtpollist --create --out list_unsig.lst tboot_mle.elt&lt;BR /&gt;
	+ lcp_crtpol2 --create --type list --ctrl 0x02 --pol owner_list.pol&lt;BR /&gt;
	+ --data owner_list.data list_unsig.lst lcp_writepol -i owner -f&lt;BR /&gt;
	+ owner_list.pol -p password&lt;BR /&gt;
	&lt;BR /&gt;
	Successfully write policy into index 0x40000001&lt;BR /&gt;
	+ cp owner_list.data /boot&lt;BR /&gt;
	+ tb_polgen --create --type nonfatal tcb.pol&lt;BR /&gt;
	+ tb_polgen --add --num 0 --pcr 18 --hash image --cmdline 'root=/dev/mapper/test--node--vg-root ro intel_iommu=on' --image /boot/vmlinuz-3.13.0-24-generic tcb.pol&lt;BR /&gt;
	+ tb_polgen --add --num 1 --pcr 19 --hash image --cmdline '' --image&lt;BR /&gt;
	+ /boot/initrd.img-3.13.0-24-generic tcb.pol lcp_writepol -i 0x20000001&lt;BR /&gt;
	+ -f tcb.pol -p password&lt;BR /&gt;
	&lt;BR /&gt;
	Successfully write policy into index 0x20000001&lt;BR /&gt;
	&lt;BR /&gt;
	&lt;BR /&gt;
	&lt;BR /&gt;
	&lt;BR /&gt;
	TBOOT: ******************* TBOOT *******************&lt;BR /&gt;
	TBOOT: 2014-01-30 12:00 +0800 1.8.0&lt;BR /&gt;
	TBOOT: *********************************************&lt;BR /&gt;
	TBOOT: command line: logging=serial,vga,memory&lt;BR /&gt;
	TBOOT: BSP is cpu 0&lt;BR /&gt;
	TBOOT: original e820 map:&lt;BR /&gt;
	TBOOT: 0000000000000000 - 000000000009bc00 (1)&lt;BR /&gt;
	TBOOT: 000000000009bc00 - 00000000000a0000 (2)&lt;BR /&gt;
	TBOOT: 00000000000e0000 - 0000000000100000 (2)&lt;BR /&gt;
	TBOOT: 0000000000100000 - 00000000bbdc7000 (1)&lt;BR /&gt;
	TBOOT: 00000000bbdc7000 - 00000000be782000 (2)&lt;BR /&gt;
	TBOOT: 00000000be782000 - 00000000be788000 (4)&lt;BR /&gt;
	TBOOT: 00000000be788000 - 00000000be8be000 (2)&lt;BR /&gt;
	TBOOT: 00000000be8be000 - 00000000be8c2000 (4)&lt;BR /&gt;
	TBOOT: 00000000be8c2000 - 00000000be8e3000 (2)&lt;BR /&gt;
	TBOOT: 00000000be8e3000 - 00000000be8e4000 (4)&lt;BR /&gt;
	TBOOT: 00000000be8e4000 - 00000000be905000 (2)&lt;BR /&gt;
	TBOOT: 00000000be905000 - 00000000be915000 (4)&lt;BR /&gt;
	TBOOT: 00000000be915000 - 00000000be925000 (2)&lt;BR /&gt;
	TBOOT: 00000000be925000 - 00000000beb2f000 (4)&lt;BR /&gt;
	TBOOT: 00000000beb2f000 - 00000000bebf0000 (3)&lt;BR /&gt;
	TBOOT: 00000000bebf0000 - 00000000bec00000 (1)&lt;BR /&gt;
	TBOOT: 00000000bec00000 - 00000000c0000000 (2)&lt;BR /&gt;
	TBOOT: 00000000f8000000 - 00000000fc000000 (2)&lt;BR /&gt;
	TBOOT: 00000000fec00000 - 00000000fec01000 (2)&lt;BR /&gt;
	TBOOT: 00000000fed19000 - 00000000fed1a000 (2)&lt;BR /&gt;
	TBOOT: 00000000fed1c000 - 00000000fed20000 (2)&lt;BR /&gt;
	TBOOT: 00000000fee00000 - 00000000fee01000 (2)&lt;BR /&gt;
	TBOOT: 00000000ff400000 - 0000000100000000 (2)&lt;BR /&gt;
	TBOOT: 0000000100000000 - 0000000440000000 (1)&lt;BR /&gt;
	TBOOT: TPM: TPM Family 0x3&lt;BR /&gt;
	TBOOT: TPM is ready&lt;BR /&gt;
	TBOOT: TPM nv_locked: TRUE&lt;BR /&gt;
	TBOOT: TPM timeout values: A: 750, B: 750, C: 750, D: 750&lt;BR /&gt;
	TBOOT: Wrong timeout B, fallback to 2000&lt;BR /&gt;
	TBOOT: Wrong timeout C, fallback to 75000&lt;BR /&gt;
	TBOOT: reading Verified Launch Policy from TPM NV...&lt;BR /&gt;
	TBOOT: :512 bytes read&lt;BR /&gt;
	TBOOT: policy:&lt;BR /&gt;
	TBOOT: version: 2&lt;BR /&gt;
	TBOOT: policy_type: TB_POLTYPE_CONT_NON_FATAL&lt;BR /&gt;
	TBOOT: hash_alg: TB_HALG_SHA1&lt;BR /&gt;
	TBOOT: policy_control: 00000001 (EXTEND_PCR17)&lt;BR /&gt;
	TBOOT: num_entries: 2&lt;BR /&gt;
	TBOOT: policy entry[0]:&lt;BR /&gt;
	TBOOT: mod_num: 0&lt;BR /&gt;
	TBOOT: pcr: 18&lt;BR /&gt;
	TBOOT: hash_type: TB_HTYPE_IMAGE&lt;BR /&gt;
	TBOOT: num_hashes: 1&lt;BR /&gt;
	TBOOT: hashes[0]: d4 63 4c 11 a3 0f a3 ee a1 dc 4d 34 98 f8 99 f6 46 51 ca da&lt;BR /&gt;
	TBOOT: policy entry[1]:&lt;BR /&gt;
	TBOOT: mod_num: 1&lt;BR /&gt;
	TBOOT: pcr: 19&lt;BR /&gt;
	TBOOT: hash_type: TB_HTYPE_IMAGE&lt;BR /&gt;
	TBOOT: num_hashes: 1&lt;BR /&gt;
	TBOOT: hashes[0]: 00 ee 09 19 c8 57 c2 12 ce 23 0a 20 02 b8 10 8f 74 18 0f 60&lt;BR /&gt;
	TBOOT: IA32_FEATURE_CONTROL_MSR: 0000ff07&lt;BR /&gt;
	TBOOT: CPU is SMX-capable&lt;BR /&gt;
	TBOOT: CPU is VMX-capable&lt;BR /&gt;
	TBOOT: SMX is enabled&lt;BR /&gt;
	TBOOT: TXT chipset and all needed capabilities present&lt;BR /&gt;
	TBOOT: TXT.ERRORCODE: 0xc0001c41&lt;BR /&gt;
	TBOOT: AC module error : acm_type=0x1, progress=0x04, error=0x7&lt;BR /&gt;
	TBOOT: TXT.ESTS: 0x0&lt;BR /&gt;
	TBOOT: TXT.E2STS: 0xc&lt;BR /&gt;
	TBOOT: IA32_FEATURE_CONTROL_MSR: 0000ff07&lt;BR /&gt;
	TBOOT: CPU is SMX-capable&lt;BR /&gt;
	TBOOT: CPU is VMX-capable&lt;BR /&gt;
	TBOOT: SMX is enabled&lt;BR /&gt;
	TBOOT: TXT chipset and all needed capabilities present&lt;BR /&gt;
	TBOOT: TXT.HEAP.BASE: 0xbef20000&lt;BR /&gt;
	TBOOT: TXT.HEAP.SIZE: 0xe0000 (917504)&lt;BR /&gt;
	TBOOT: bios_data (@0xbef20008, 0x56):&lt;BR /&gt;
	TBOOT: version: 4&lt;BR /&gt;
	TBOOT: bios_sinit_size: 0xce40 (52800)&lt;BR /&gt;
	TBOOT: lcp_pd_base: 0x0&lt;BR /&gt;
	TBOOT: lcp_pd_size: 0x0 (0)&lt;BR /&gt;
	TBOOT: num_logical_procs: 8&lt;BR /&gt;
	TBOOT: flags: 0x00000000&lt;BR /&gt;
	TBOOT: ext_data_elts[]:&lt;BR /&gt;
	TBOOT: BIOS_SPEC_VER:&lt;BR /&gt;
	TBOOT: major: 0x2&lt;BR /&gt;
	TBOOT: minor: 0x1&lt;BR /&gt;
	TBOOT: rev: 0x0&lt;BR /&gt;
	TBOOT: ACM:&lt;BR /&gt;
	TBOOT: num_acms: 1&lt;BR /&gt;
	TBOOT: acm_addrs[0]: 0xfff7d000&lt;BR /&gt;
	TBOOT: CR0 and EFLAGS OK&lt;BR /&gt;
	TBOOT: supports preserving machine check errors&lt;BR /&gt;
	TBOOT: CPU is ready for SENTER&lt;BR /&gt;
	TBOOT: checking previous errors on the last boot.&lt;BR /&gt;
	last boot has error.&lt;BR /&gt;
	TBOOT: checking if module /4th_gen_i5_i7_SINIT_75.BIN is an SINIT for this platform...&lt;BR /&gt;
	TBOOT: chipset production fused: 1&lt;BR /&gt;
	TBOOT: chipset ids: vendor: 0x8086, device: 0xb002, revision: 0x1&lt;BR /&gt;
	TBOOT: processor family/model/stepping: 0x306c3&lt;BR /&gt;
	TBOOT: platform id: 0x4000000000000&lt;BR /&gt;
	TBOOT: 1 ACM chipset id entries:&lt;BR /&gt;
	TBOOT: vendor: 0x8086, device: 0xb002, flags: 0x1, revision: 0x1, extended: 0x0&lt;BR /&gt;
	TBOOT: 3 ACM processor id entries:&lt;BR /&gt;
	TBOOT: fms: 0x306c0, fms_mask: 0xfff3ff0, platform_id: 0x0, platform_mask: 0x0&lt;BR /&gt;
	TBOOT: SINIT matches platform&lt;BR /&gt;
	TBOOT: TXT.SINIT.BASE: 0xbef00000&lt;BR /&gt;
	TBOOT: TXT.SINIT.SIZE: 0x20000 (131072)&lt;BR /&gt;
	TBOOT: BIOS has already loaded an SINIT module&lt;BR /&gt;
	TBOOT: 1 ACM chipset id entries:&lt;BR /&gt;
	TBOOT: vendor: 0x8086, device: 0xb002, flags: 0x1, revision: 0x1, extended: 0x0&lt;BR /&gt;
	TBOOT: 3 ACM processor id entries:&lt;BR /&gt;
	TBOOT: fms: 0x306c0, fms_mask: 0xfff3ff0, platform_id: 0x0, platform_mask: 0x0&lt;BR /&gt;
	TBOOT: BIOS-provided SINIT is older: date=20130612&lt;BR /&gt;
	TBOOT: copied SINIT (size=ce40) to 0xbef00000&lt;BR /&gt;
	TBOOT: AC mod base alignment OK&lt;BR /&gt;
	TBOOT: AC mod size OK&lt;BR /&gt;
	TBOOT: AC module header dump for SINIT:&lt;BR /&gt;
	TBOOT: type: 0x2 (ACM_TYPE_CHIPSET)&lt;BR /&gt;
	TBOOT: subtype: 0x0&lt;BR /&gt;
	TBOOT: length: 0xa1 (161)&lt;BR /&gt;
	TBOOT: version: 0&lt;BR /&gt;
	TBOOT: chipset_id: 0xb002&lt;BR /&gt;
	TBOOT: flags: 0x0&lt;BR /&gt;
	TBOOT: pre_production: 0&lt;BR /&gt;
	TBOOT: debug_signed: 0&lt;BR /&gt;
	TBOOT: vendor: 0x8086&lt;BR /&gt;
	TBOOT: date: 0x20130712&lt;BR /&gt;
	TBOOT: size*4: 0xce40 (52800)&lt;BR /&gt;
	TBOOT: code_control: 0x0&lt;BR /&gt;
	TBOOT: entry point: 0x00000008:000062dc&lt;BR /&gt;
	TBOOT: scratch_size: 0x8f (143)&lt;BR /&gt;
	TBOOT: info_table:&lt;BR /&gt;
	TBOOT: uuid: {0x7fc03aaa, 0x46a7, 0x18db, 0xac2e,&lt;BR /&gt;
	{0x69, 0x8f, 0x8d, 0x41, 0x7f, 0x5a}}&lt;BR /&gt;
	TBOOT: ACM_UUID_V3&lt;BR /&gt;
	TBOOT: chipset_acm_type: 0x1 (SINIT)&lt;BR /&gt;
	TBOOT: version: 4&lt;BR /&gt;
	TBOOT: length: 0x2c (44)&lt;BR /&gt;
	TBOOT: chipset_id_list: 0x4ec&lt;BR /&gt;
	TBOOT: os_sinit_data_ver: 0x6&lt;BR /&gt;
	TBOOT: min_mle_hdr_ver: 0x00020000&lt;BR /&gt;
	TBOOT: capabilities: 0x0000002e&lt;BR /&gt;
	TBOOT: rlp_wake_getsec: 0&lt;BR /&gt;
	TBOOT: rlp_wake_monitor: 1&lt;BR /&gt;
	TBOOT: ecx_pgtbl: 1&lt;BR /&gt;
	TBOOT: stm: 1&lt;BR /&gt;
	TBOOT: pcr_map_no_legacy: 0&lt;BR /&gt;
	TBOOT: pcr_map_da: 1&lt;BR /&gt;
	TBOOT: platform_type: 0&lt;BR /&gt;
	TBOOT: max_phy_addr: 0&lt;BR /&gt;
	TBOOT: acm_ver: 75&lt;BR /&gt;
	TBOOT: chipset list:&lt;BR /&gt;
	TBOOT: count: 1&lt;BR /&gt;
	TBOOT: entry 0:&lt;BR /&gt;
	TBOOT: flags: 0x1&lt;BR /&gt;
	TBOOT: vendor_id: 0x8086&lt;BR /&gt;
	TBOOT: device_id: 0xb002&lt;BR /&gt;
	TBOOT: revision_id: 0x1&lt;BR /&gt;
	TBOOT: extended_id: 0x0&lt;BR /&gt;
	TBOOT: processor list:&lt;BR /&gt;
	TBOOT: count: 3&lt;BR /&gt;
	TBOOT: entry 0:&lt;BR /&gt;
	TBOOT: fms: 0x306c0&lt;BR /&gt;
	TBOOT: fms_mask: 0xfff3ff0&lt;BR /&gt;
	TBOOT: platform_id: 0x0&lt;BR /&gt;
	TBOOT: platform_mask: 0x0&lt;BR /&gt;
	TBOOT: entry 1:&lt;BR /&gt;
	TBOOT: fms: 0x40660&lt;BR /&gt;
	TBOOT: fms_mask: 0xfff3ff0&lt;BR /&gt;
	TBOOT: platform_id: 0x0&lt;BR /&gt;
	TBOOT: platform_mask: 0x0&lt;BR /&gt;
	TBOOT: entry 2:&lt;BR /&gt;
	TBOOT: fms: 0x40650&lt;BR /&gt;
	TBOOT: fms_mask: 0xfff3ff0&lt;BR /&gt;
	TBOOT: platform_id: 0x0&lt;BR /&gt;
	TBOOT: platform_mask: 0x0&lt;BR /&gt;
	TBOOT: file addresses:&lt;BR /&gt;
	TBOOT: &amp;amp;_start=0x804000&lt;BR /&gt;
	TBOOT: &amp;amp;_end=0xac6460&lt;BR /&gt;
	TBOOT: &amp;amp;_mle_start=0x804000&lt;BR /&gt;
	TBOOT: &amp;amp;_mle_end=0x834000&lt;BR /&gt;
	TBOOT: &amp;amp;_post_launch_entry=0x804010&lt;BR /&gt;
	TBOOT: &amp;amp;_txt_wakeup=0x8041f0&lt;BR /&gt;
	TBOOT: &amp;amp;g_mle_hdr=0x81b5a0&lt;BR /&gt;
	TBOOT: MLE header:&lt;BR /&gt;
	TBOOT: uuid={0x9082ac5a, 0x476f, 0x74a7, 0x5c0f,&lt;BR /&gt;
	{0x55, 0xa2, 0xcb, 0x51, 0xb6, 0x42}}&lt;BR /&gt;
	TBOOT: length=34&lt;BR /&gt;
	TBOOT: version=00020001&lt;BR /&gt;
	TBOOT: entry_point=00000010&lt;BR /&gt;
	TBOOT: first_valid_page=00000000&lt;BR /&gt;
	TBOOT: mle_start_off=4000&lt;BR /&gt;
	TBOOT: mle_end_off=34000&lt;BR /&gt;
	TBOOT: capabilities: 0x00000027&lt;BR /&gt;
	TBOOT: rlp_wake_getsec: 1&lt;BR /&gt;
	TBOOT: rlp_wake_monitor: 1&lt;BR /&gt;
	TBOOT: ecx_pgtbl: 1&lt;BR /&gt;
	TBOOT: stm: 0&lt;BR /&gt;
	TBOOT: pcr_map_no_legacy: 0&lt;BR /&gt;
	TBOOT: pcr_map_da: 1&lt;BR /&gt;
	TBOOT: platform_type: 0&lt;BR /&gt;
	TBOOT: max_phy_addr: 0&lt;BR /&gt;
	TBOOT: MLE start=804000, end=834000, size=30000&lt;BR /&gt;
	TBOOT: ptab_size=3000, ptab_base=0x801000&lt;BR /&gt;
	TBOOT: TXT.HEAP.BASE: 0xbef20000&lt;BR /&gt;
	TBOOT: TXT.HEAP.SIZE: 0xe0000 (917504)&lt;BR /&gt;
	TBOOT: bios_data (@0xbef20008, 0x56):&lt;BR /&gt;
	TBOOT: version: 4&lt;BR /&gt;
	TBOOT: bios_sinit_size: 0xce40 (52800)&lt;BR /&gt;
	TBOOT: lcp_pd_base: 0x0&lt;BR /&gt;
	TBOOT: lcp_pd_size: 0x0 (0)&lt;BR /&gt;
	TBOOT: num_logical_procs: 8&lt;BR /&gt;
	TBOOT: flags: 0x00000000&lt;BR /&gt;
	TBOOT: ext_data_elts[]:&lt;BR /&gt;
	TBOOT: BIOS_SPEC_VER:&lt;BR /&gt;
	TBOOT: major: 0x2&lt;BR /&gt;
	TBOOT: minor: 0x1&lt;BR /&gt;
	TBOOT: rev: 0x0&lt;BR /&gt;
	TBOOT: ACM:&lt;BR /&gt;
	TBOOT: num_acms: 1&lt;BR /&gt;
	TBOOT: acm_addrs[0]: 0xfff7d000&lt;BR /&gt;
	TBOOT: discarding RAM above reserved regions: 0xbebf0000 - 0xbec00000&lt;BR /&gt;
	TBOOT: min_lo_ram: 0x0, max_lo_ram: 0xbbdc7000&lt;BR /&gt;
	TBOOT: min_hi_ram: 0x100000000, max_hi_ram: 0x440000000&lt;BR /&gt;
	TBOOT: no LCP module found&lt;BR /&gt;
	TBOOT: os_sinit_data (@0xbef3517e, 0x7c):&lt;BR /&gt;
	TBOOT: version: 6&lt;BR /&gt;
	TBOOT: flags: 0&lt;BR /&gt;
	TBOOT: mle_ptab: 0x801000&lt;BR /&gt;
	TBOOT: mle_size: 0x30000 (196608)&lt;BR /&gt;
	TBOOT: mle_hdr_base: 0x175a0&lt;BR /&gt;
	TBOOT: vtd_pmr_lo_base: 0x0&lt;BR /&gt;
	TBOOT: vtd_pmr_lo_size: 0xbbc00000&lt;BR /&gt;
	TBOOT: vtd_pmr_hi_base: 0x100000000&lt;BR /&gt;
	TBOOT: vtd_pmr_hi_size: 0x340000000&lt;BR /&gt;
	TBOOT: lcp_po_base: 0x0&lt;BR /&gt;
	TBOOT: lcp_po_size: 0x0 (0)&lt;BR /&gt;
	TBOOT: capabilities: 0x00000002&lt;BR /&gt;
	TBOOT: rlp_wake_getsec: 0&lt;BR /&gt;
	TBOOT: rlp_wake_monitor: 1&lt;BR /&gt;
	TBOOT: ecx_pgtbl: 0&lt;BR /&gt;
	TBOOT: stm: 0&lt;BR /&gt;
	TBOOT: pcr_map_no_legacy: 0&lt;BR /&gt;
	TBOOT: pcr_map_da: 0&lt;BR /&gt;
	TBOOT: platform_type: 0&lt;BR /&gt;
	TBOOT: max_phy_addr: 0&lt;BR /&gt;
	TBOOT: efi_rsdt_ptr: 0x0&lt;BR /&gt;
	TBOOT: ext_data_elts[]:&lt;BR /&gt;
	TBOOT: EVENT_LOG_POINTER:&lt;BR /&gt;
	TBOOT: size: 16&lt;BR /&gt;
	TBOOT: elog_addr: 0xbef30176&lt;BR /&gt;
	TBOOT: Event Log Container:&lt;BR /&gt;
	TBOOT: Signature: TXT Event Container&lt;BR /&gt;
	TBOOT: ContainerVer: 1.0&lt;BR /&gt;
	TBOOT: PCREventVer: 1.0&lt;BR /&gt;
	TBOOT: Size: 20480&lt;BR /&gt;
	TBOOT: EventsOffset: [48,48)&lt;BR /&gt;
	TBOOT: setting MTRRs for acmod: base=0xbef00000, size=0xce40, num_pages=13&lt;BR /&gt;
	TBOOT: executing GETSEC[SENTER]...&lt;/P&gt;</description>
      <pubDate>Wed, 21 May 2014 17:47:04 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Archive/error-code-0xc0001c41/m-p/1020118#M37838</guid>
      <dc:creator>Dieter_K_</dc:creator>
      <dc:date>2014-05-21T17:47:04Z</dc:date>
    </item>
    <item>
      <title>You are using an SINIT file</title>
      <link>https://community.intel.com/t5/Software-Archive/error-code-0xc0001c41/m-p/1020119#M37839</link>
      <description>&lt;P&gt;You are using an SINIT file for a core i5/ core i7 CPU. &amp;nbsp;You need one of the Server SINIT files, however I do not see an SINIT file that looks like it would work with your CPU. I am asking the TXT engineers about this.&lt;/P&gt;

&lt;P&gt;Here is the repository of SINIT files: &lt;A href="https://software.intel.com/en-us/articles/intel-trusted-execution-technology/" target="_blank"&gt;https://software.intel.com/en-us/articles/intel-trusted-execution-technology/&lt;/A&gt;&lt;/P&gt;

&lt;P&gt;&amp;nbsp;&lt;/P&gt;

&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Fri, 23 May 2014 20:30:41 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Archive/error-code-0xc0001c41/m-p/1020119#M37839</guid>
      <dc:creator>Gael_H_Intel</dc:creator>
      <dc:date>2014-05-23T20:30:41Z</dc:date>
    </item>
    <item>
      <title> </title>
      <link>https://community.intel.com/t5/Software-Archive/error-code-0xc0001c41/m-p/1020120#M37840</link>
      <description>&lt;P&gt;&amp;nbsp;&lt;/P&gt;

&lt;P&gt;There are a couple things to look at: &amp;nbsp;The&amp;nbsp;&lt;SPAN style="font-size: 1em; line-height: 1.5;"&gt;Xeon E3-1265L uses the Ivy Bridge 3rd_gen_i5_i7_SINIT_67.BIN and you are using the 4th gen bin file. &amp;nbsp;If changing that doesn't work here are some more things to look at:&lt;/SPAN&gt;&lt;/P&gt;

&lt;OL&gt;
	&lt;LI&gt;Please provide the created policy files, since tboot 1.8.0 has bug in lcptools.&lt;/LI&gt;
	&lt;LI&gt;Use tboot 1.8.1 lcptools or simply remove the owner index to verify whether it is caused by the wrong lcp policy. (wrong lcp policy procuded by tboot 1.8.0 should lead to&amp;nbsp;&lt;SPAN style="font-size: 1em; line-height: 1.5;"&gt;a error code 0xC0001D01(Wrong LCP data integrity).&lt;/SPAN&gt;&lt;/LI&gt;
	&lt;LI&gt;Is there a BIOS update from your vendor?&amp;nbsp;&lt;/LI&gt;
&lt;/OL&gt;</description>
      <pubDate>Tue, 27 May 2014 15:21:05 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Archive/error-code-0xc0001c41/m-p/1020120#M37840</guid>
      <dc:creator>Gael_H_Intel</dc:creator>
      <dc:date>2014-05-27T15:21:05Z</dc:date>
    </item>
    <item>
      <title>Could you check whether your</title>
      <link>https://community.intel.com/t5/Software-Archive/error-code-0xc0001c41/m-p/1020121#M37841</link>
      <description>&lt;P&gt;Could you check whether your processor e3-1265L is a v2 or v3? &amp;nbsp;(and similarly &amp;nbsp;check on the board there should be a v#- most &amp;nbsp;RPL were s1200v3RPL. And could you please tell me how you chose which SINIT version to run?&amp;nbsp;&lt;BR /&gt;
	I'm also trying to confirm the SINIT bin version. Will update here when confirmed.&lt;/P&gt;

&lt;P&gt;&lt;U&gt;UPDATE/CORRECTION:&amp;nbsp;&lt;/U&gt; AXXTPME3 922115 is apparently the required TPM for the v3 boards/single XEON processor..&lt;/P&gt;</description>
      <pubDate>Thu, 03 Jul 2014 23:01:00 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Archive/error-code-0xc0001c41/m-p/1020121#M37841</guid>
      <dc:creator>Colleen_C_Intel</dc:creator>
      <dc:date>2014-07-03T23:01:00Z</dc:date>
    </item>
    <item>
      <title>Recap of latest info:  </title>
      <link>https://community.intel.com/t5/Software-Archive/error-code-0xc0001c41/m-p/1020122#M37842</link>
      <description>&lt;P&gt;Recap of latest info: &amp;nbsp;&lt;BR /&gt;
	&amp;nbsp;-&amp;nbsp; CORRECTION: This was later corrected to AXXTPMe3 #&lt;SPAN style="font: 12.22px/20px Arial, 宋体, Tahoma, Helvetica, sans-serif; color: rgb(83, 87, 94); text-transform: none; text-indent: 0px; letter-spacing: normal; word-spacing: 0px; float: none; display: inline !important; white-space: normal; font-size-adjust: none; font-stretch: normal; background-color: rgb(255, 255, 255); -webkit-text-stroke-width: 0px;"&gt;922115, not 912429)&lt;/SPAN&gt;&lt;BR /&gt;
	&lt;SPAN style="font-family: Consolas, &amp;quot;Lucida Console&amp;quot;, Menlo, Monaco, &amp;quot;DejaVu Sans Mono&amp;quot;, monospace, sans-serif;"&gt;- if there's any chance that an 'earlier than 67 bin' was ever used, you need to run the revocation tool to remove earlier version (RACM at &lt;/SPAN&gt;&lt;A href="https://software.intel.com/protected-download/267276/183305"&gt;https://software.intel.com/protected-download/267276/183305&lt;/A&gt;&lt;SPAN style="font-family: Consolas, &amp;quot;Lucida Console&amp;quot;, Menlo, Monaco, &amp;quot;DejaVu Sans Mono&amp;quot;, monospace, sans-serif;"&gt;) and bring up to post 67 version.(as in BIOS 02.01.0002/4&lt;/SPAN&gt;&lt;BR /&gt;
	&lt;SPAN style="line-height: 1.5; font-size: 1em;"&gt;&amp;nbsp;- Use Bios&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN style="line-height: 1.5; font-family: Consolas, &amp;quot;Lucida Console&amp;quot;, Menlo, Monaco, &amp;quot;DejaVu Sans Mono&amp;quot;, monospace, sans-serif; font-size: 1em;"&gt;02.01.0004, but be sure you had loaded&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN style="line-height: 1.5; font-family: Consolas, &amp;quot;Lucida Console&amp;quot;, Menlo, Monaco, &amp;quot;DejaVu Sans Mono&amp;quot;, monospace, sans-serif; font-size: 1em;"&gt;02.01.0002 before loading 0004.&amp;nbsp;&lt;/SPAN&gt;&lt;BR /&gt;
	&lt;SPAN style="line-height: 1.5; font-family: Consolas, &amp;quot;Lucida Console&amp;quot;, Menlo, Monaco, &amp;quot;DejaVu Sans Mono&amp;quot;, monospace, sans-serif; font-size: 1em;"&gt;- try reprovisioning&lt;BR /&gt;
	- the 4th gen i5/i7 error codes are the ones to use.&amp;nbsp;&lt;BR /&gt;
	Please attach log if you still receive the&amp;nbsp;&lt;/SPAN&gt;0xc0001c41&amp;nbsp;(or any other) error.&lt;/P&gt;

&lt;P&gt;Also - please let us know if you ever had this S1200 TPM/TXT running without error.&lt;/P&gt;

&lt;P&gt;&lt;BR /&gt;
	&amp;nbsp;&lt;/P&gt;

&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Fri, 04 Jul 2014 06:27:00 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Archive/error-code-0xc0001c41/m-p/1020122#M37842</guid>
      <dc:creator>Colleen_C_Intel</dc:creator>
      <dc:date>2014-07-04T06:27:00Z</dc:date>
    </item>
    <item>
      <title>The invalid index often means</title>
      <link>https://community.intel.com/t5/Software-Archive/error-code-0xc0001c41/m-p/1020123#M37843</link>
      <description>&lt;P&gt;The invalid index often means that one of the critical indexes wasn't setup by the OEM and you have to do it. Look at tpmnv_defindex.&lt;/P&gt;

&lt;P&gt;....JW&lt;/P&gt;

&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Mon, 07 Jul 2014 18:05:14 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Archive/error-code-0xc0001c41/m-p/1020123#M37843</guid>
      <dc:creator>John_M_2</dc:creator>
      <dc:date>2014-07-07T18:05:14Z</dc:date>
    </item>
    <item>
      <title>try tpmnv_getcap - it will</title>
      <link>https://community.intel.com/t5/Software-Archive/error-code-0xc0001c41/m-p/1020124#M37844</link>
      <description>&lt;P&gt;try tpmnv_getcap - it will spout all the indexes that have been defined - I think the one I was missing was 0x20000001. It looks like that's what your error code is saying as well - I have a different processor and my codes are different so try the index, but disregard the message about the incorrect driver parameter.&lt;/P&gt;

&lt;P&gt;....JW&lt;/P&gt;</description>
      <pubDate>Mon, 07 Jul 2014 19:25:00 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Archive/error-code-0xc0001c41/m-p/1020124#M37844</guid>
      <dc:creator>John_M_2</dc:creator>
      <dc:date>2014-07-07T19:25:00Z</dc:date>
    </item>
    <item>
      <title>Yes I saw that - the size I</title>
      <link>https://community.intel.com/t5/Software-Archive/error-code-0xc0001c41/m-p/1020125#M37845</link>
      <description>&lt;P&gt;Yes I saw that - the size I have in the policy files is 256 - did you have 512 in yours?&lt;/P&gt;

&lt;P&gt;I doubt that's the problem - after around 4 weeks of running around i have only moved forward by running the utilities - I think in this case it was readpol - in a debugger and watching what was setting it off. So when it trys to get info from an index you can see which onee.&lt;/P&gt;

&lt;P&gt;The other method is putting printks in tboot. - that (should) cause the trusted boot to fail (since tboot is modified) but you should be able to get far enough to see which index it's complaining about - all that happens before GETSEC[SENTER]&lt;/P&gt;

&lt;P&gt;....JW&lt;/P&gt;</description>
      <pubDate>Mon, 07 Jul 2014 19:48:29 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Archive/error-code-0xc0001c41/m-p/1020125#M37845</guid>
      <dc:creator>John_M_2</dc:creator>
      <dc:date>2014-07-07T19:48:29Z</dc:date>
    </item>
    <item>
      <title>CORRECTION: </title>
      <link>https://community.intel.com/t5/Software-Archive/error-code-0xc0001c41/m-p/1020126#M37846</link>
      <description>&lt;P&gt;&lt;STRONG&gt;CORRECTION&lt;/STRONG&gt;:&amp;nbsp;&lt;BR /&gt;
	The TPM that has&amp;nbsp;been tested with the Intel(R)&amp;nbsp;S1200v3RP board with the above listed processor v3 (HSW) is the second version of the AXXTPMe3 (MM#922115;&amp;nbsp; TA#G20697-003 or higher -00x;&amp;nbsp;&amp;nbsp;PBA# G12756-104 or later -00#).&amp;nbsp;&lt;BR /&gt;
	This version was announced by Intel in PCN 111453 and 113080&lt;BR /&gt;
	Note: &amp;nbsp; (Earlier posts by me have also been corrected above to avoid confusing&amp;nbsp;anyone reading this thread once archived)&lt;/P&gt;

&lt;P&gt;The latest BIOS for the board contains the correct SINIT binary.&lt;/P&gt;</description>
      <pubDate>Tue, 08 Jul 2014 05:28:25 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Archive/error-code-0xc0001c41/m-p/1020126#M37846</guid>
      <dc:creator>Colleen_C_Intel</dc:creator>
      <dc:date>2014-07-08T05:28:25Z</dc:date>
    </item>
    <item>
      <title>Deiter - I never said that</title>
      <link>https://community.intel.com/t5/Software-Archive/error-code-0xc0001c41/m-p/1020127#M37847</link>
      <description>&lt;P&gt;Deiter - I never said that tboot was causing the reboot - but there is, at least in your first post, a clear indication that there's a missing index. Which could / would cause the SENTER leaf to fail. So which index is missing, well step 1. is , which ones are defined for your platform - #tpmnv_getcap&lt;/P&gt;

&lt;P&gt;....JW&lt;/P&gt;

&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Tue, 08 Jul 2014 13:12:16 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Archive/error-code-0xc0001c41/m-p/1020127#M37847</guid>
      <dc:creator>John_M_2</dc:creator>
      <dc:date>2014-07-08T13:12:16Z</dc:date>
    </item>
    <item>
      <title>Hi Dieter,</title>
      <link>https://community.intel.com/t5/Software-Archive/error-code-0xc0001c41/m-p/1020128#M37848</link>
      <description>&lt;P&gt;Hi Dieter,&lt;BR /&gt;
	Working to see where you can get a 104. Will email you privately.&lt;/P&gt;</description>
      <pubDate>Wed, 09 Jul 2014 15:30:50 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Archive/error-code-0xc0001c41/m-p/1020128#M37848</guid>
      <dc:creator>Colleen_C_Intel</dc:creator>
      <dc:date>2014-07-09T15:30:50Z</dc:date>
    </item>
    <item>
      <title>Hi Colleen,</title>
      <link>https://community.intel.com/t5/Software-Archive/error-code-0xc0001c41/m-p/1020129#M37849</link>
      <description>&lt;P&gt;Hi Colleen,&lt;/P&gt;

&lt;P&gt;Can you email me as well?&amp;nbsp; I'm having the exact same problem as Dieter.&lt;/P&gt;</description>
      <pubDate>Sat, 12 Jul 2014 09:58:37 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Archive/error-code-0xc0001c41/m-p/1020129#M37849</guid>
      <dc:creator>I_A_1</dc:creator>
      <dc:date>2014-07-12T09:58:37Z</dc:date>
    </item>
    <item>
      <title>Hi I.A.</title>
      <link>https://community.intel.com/t5/Software-Archive/error-code-0xc0001c41/m-p/1020130#M37850</link>
      <description>&lt;P&gt;Hi I.A.&lt;/P&gt;

&lt;P&gt;I don't have your email address in this thread.....Can you tell me what system and what processor you have &amp;nbsp;(include any v#s in the names please).&lt;/P&gt;</description>
      <pubDate>Mon, 14 Jul 2014 16:10:59 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Archive/error-code-0xc0001c41/m-p/1020130#M37850</guid>
      <dc:creator>Colleen_C_Intel</dc:creator>
      <dc:date>2014-07-14T16:10:59Z</dc:date>
    </item>
    <item>
      <title>Board support owner has</title>
      <link>https://community.intel.com/t5/Software-Archive/error-code-0xc0001c41/m-p/1020131#M37851</link>
      <description>&lt;P&gt;Board support owner has confirmed that documentation will be updated to show the later version of AXXTPMe3. MM#&amp;nbsp;&lt;SPAN style="font-size: 12.222222328186035px; line-height: 20px;"&gt;922115&lt;/SPAN&gt;&lt;/P&gt;

&lt;P&gt;Supplies of AXXTPME3/&lt;SPAN style="font-size: 12.222222328186035px; line-height: 20px;"&gt;922115 are being replenished with shipments going out this week (mid July 2014). &amp;nbsp;Please recheck with suppliers in the next week.&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;

&lt;P&gt;Update - #922115 is confirmed to fix this issue on the S1200v3RP board.&lt;/P&gt;</description>
      <pubDate>Tue, 15 Jul 2014 15:07:00 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Archive/error-code-0xc0001c41/m-p/1020131#M37851</guid>
      <dc:creator>Colleen_C_Intel</dc:creator>
      <dc:date>2014-07-15T15:07:00Z</dc:date>
    </item>
    <item>
      <title>Hi Dieter, </title>
      <link>https://community.intel.com/t5/Software-Archive/error-code-0xc0001c41/m-p/1020132#M37852</link>
      <description>&lt;P&gt;Hi Dieter,&amp;nbsp;&lt;/P&gt;

&lt;P&gt;The only thought would be reset thru BIOS and if you can't get into that (they system wasn't set up so you could use a console remoted in was it? &amp;nbsp;&lt;BR /&gt;
	I need to ask you to try taking this through Intel Customer Support for Server Boards to get you into the BIOS. I believe the phone number for Germany is&amp;nbsp;&lt;STRONG&gt;069 9509 6099, &lt;/STRONG&gt;or check the Intel.com web site under contact support.&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Mon, 08 Sep 2014 22:51:59 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Archive/error-code-0xc0001c41/m-p/1020132#M37852</guid>
      <dc:creator>Colleen_C_Intel</dc:creator>
      <dc:date>2014-09-08T22:51:59Z</dc:date>
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  </channel>
</rss>

