topic I downloaded and compile in Software Archive

Software Controlled Clock Facilities

Wei — Tue, 21 Oct 2014 23:35:41 GMT

Hi,

I am trying to control the duty cycle of mic cores (through IA32_CLOCK_MODULATION), but I just found the following limited information in the Developer's Guide.

"The processor implements internal MSRs (IA32_THERM_STATUS, IA32_THERM_INTERRUPT,
IA32_CLOCK_MODULATION) that allow the processor temperature to be monitored and the processor performance to
be modulated in predefined duty cycles under software control."

How could the duty cycles be software controlled on MIC? On SandyBridge (and others) one can use MSR Inline Assembly or msr device files to achieve this.

The paragraph immediately following the above confuses me a little bit:

" The Intel® Xeon PhiTM coprocessor supports non-ACPI based thermal monitoring through a dedicated TMU and a set of
thermal sensors. Thermal throttling of the core clock occurs automatically in hardware during a thermal event.
Additionally, OS power-management software is given an opportunity to modulate the core frequency and voltage in
response to the thermal event. These core frequency and voltage settings take effect when the thermal event ends. In
other words, Intel® Xeon PhiTM coprocessor hardware provides equivalent support for handling thermal events but
through different mechanisms. "

If thermal throttlin occurs automatically in hardware, will the duty cycles still controllable in software? OS power-management software can modulate core frequency and voltage, that is DVFS, can OS power-management control the duty cycle? If not, how could "the processor performance ...under software control." ?

In short, how could we software-modulate the duty cycles on MIC?

Thank you!

Wei,

TaylorIoTKidd — Thu, 23 Oct 2014 16:37:23 GMT

Wei,

From what perspective are you asking these questions? Are you taking the view of a conventional application running on top of the OS? Or are you taking the point of view of an OS designer?

The guide you mention is a "system" software developer's guide, meaning it is intended for designers of operating systems and other bare metal applications.

The power management controls you mention are not directly accessible to user applications to my knowledge.

Also, the underlying thermal monitoring hardware and controls are not as full featured as what you find in the current big core processors.

Regards
--
Taylor

Hi Taylor,

Wei — Thu, 23 Oct 2014 17:12:07 GMT

Hi Taylor,

Thank you for your reply.

I am asking with mixed views, with more view of a conventional application running on top of the OS. I am curious whether the MIC OS exposes any "gates" (e.g. kernel module, system call) for sudo users (or even application, when system call is exposed) to explicitly control the IA32_CLOCK_MODULATION internal MSR.

On Sandy Bridge, privileged users can explicitly set the IA32_CLOCK_MODULATION by writing to /dev/cpu/{cpu_id}/msr. To support user control (with pros and cons), kernels can be modified to add system call that executes the wrmsr inline assembly to set the IA32_CLOCK_MODULATION.

I noticed on MIC there is the same device file for each core as SandyBridge (/dev/cpu/{cpu_id}/msr). I am wondering can a sudo user set the IA32_CLOCK_MODULATION on MIC?

Thank you!

Wei

I downloaded and compile

Wei — Thu, 23 Oct 2014 21:09:31 GMT

I downloaded and compile/built a rdmsr version for MIC (https://01.org/msr-tools/downloads).

The following are results of read msr 0x10 and 0x19a. 0x19a is the register number for IA32_CLOCK_MODULATION on architectures like SandyBridge.

[root@savina-mic0 bin]# ./rdmsr 0x10
4c16258f3c3
[root@savina-mic0 bin]# ./rdmsr 0x19a
rdmsr: CPU 0 cannot read MSR 0x0000019a

It seems the /dev/cpu/0/msr does not have the 0x19a counter.