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    <title>topic John, in Software Archive</title>
    <link>https://community.intel.com/t5/Software-Archive/mpi-program/m-p/1033333#M42940</link>
    <description>&lt;P&gt;John,&lt;/P&gt;

&lt;P&gt;Thanks for the reference.&lt;/P&gt;

&lt;P&gt;Regards&lt;BR /&gt;
	--&lt;BR /&gt;
	Taylor&lt;BR /&gt;
	&amp;nbsp;&lt;/P&gt;</description>
    <pubDate>Thu, 23 Oct 2014 17:57:26 GMT</pubDate>
    <dc:creator>TaylorIoTKidd</dc:creator>
    <dc:date>2014-10-23T17:57:26Z</dc:date>
    <item>
      <title>mpi program</title>
      <link>https://community.intel.com/t5/Software-Archive/mpi-program/m-p/1033329#M42936</link>
      <description>&lt;P&gt;is it possible to run an mpi program with processes on&amp;nbsp;cpu and mic. for example, if I have two processes, say&amp;nbsp;rank=0 and rank=1, is it possible to run rank=0 on cpu and rank=1 on mic? if yes, could you show an example. thanks.&lt;/P&gt;</description>
      <pubDate>Thu, 23 Oct 2014 04:51:26 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Archive/mpi-program/m-p/1033329#M42936</guid>
      <dc:creator>Jen_B_</dc:creator>
      <dc:date>2014-10-23T04:51:26Z</dc:date>
    </item>
    <item>
      <title>https://software.intel.com</title>
      <link>https://community.intel.com/t5/Software-Archive/mpi-program/m-p/1033330#M42937</link>
      <description>&lt;P&gt;&lt;A href="https://software.intel.com/sites/default/files/article/336139/using-intel-mpi-on-intel-xeon-phi-coprosessor-systems-v1.3.pdf" target="_blank"&gt;https://software.intel.com/sites/default/files/article/336139/using-intel-mpi-on-intel-xeon-phi-coprosessor-systems-v1.3.pdf&lt;/A&gt;&lt;/P&gt;

&lt;P&gt;&lt;A href="https://software.intel.com/en-us/articles/how-to-run-intel-mpi-on-xeon-phi" target="_blank"&gt;https://software.intel.com/en-us/articles/how-to-run-intel-mpi-on-xeon-phi&lt;/A&gt;&lt;/P&gt;

&lt;P&gt;In order to make this useful, at least on the coprocessor side, the ranks will need to use multiple threads per rank so as to balance the work rate on host vs. coprocessor and avoid running out of memory.&amp;nbsp; That subject still seems too controversial to be posted on IDZ.&lt;/P&gt;</description>
      <pubDate>Thu, 23 Oct 2014 12:44:59 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Archive/mpi-program/m-p/1033330#M42937</guid>
      <dc:creator>TimP</dc:creator>
      <dc:date>2014-10-23T12:44:59Z</dc:date>
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    <item>
      <title>Thanks a lot!</title>
      <link>https://community.intel.com/t5/Software-Archive/mpi-program/m-p/1033331#M42938</link>
      <description>&lt;P&gt;Thanks&amp;nbsp;a lot!&lt;/P&gt;</description>
      <pubDate>Thu, 23 Oct 2014 13:30:52 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Archive/mpi-program/m-p/1033331#M42938</guid>
      <dc:creator>Jen_B_</dc:creator>
      <dc:date>2014-10-23T13:30:52Z</dc:date>
    </item>
    <item>
      <title>I don't know why anyone would</title>
      <link>https://community.intel.com/t5/Software-Archive/mpi-program/m-p/1033332#M42939</link>
      <description>&lt;P&gt;I don't know why anyone would consider the combination of "symmetric mode" (some MPI tasks on host(s) and some on Xeon Phi) with hybrid parallelism (MPI + threads) to be controversial?&amp;nbsp;&amp;nbsp;&lt;/P&gt;

&lt;P&gt;In addition to the many excellent references on the Intel web site, you might find the Xeon Phi training material at TACC to be useful.&amp;nbsp;&amp;nbsp; Look for "symmetric" in the course materials at &lt;A href="https://www.tacc.utexas.edu/user-services/training/course-materials.&amp;nbsp;&amp;nbsp;" target="_blank"&gt;https://www.tacc.utexas.edu/user-services/training/course-materials.&amp;nbsp;&amp;nbsp;&lt;/A&gt;; The TACC training material is somewhat site-specific, but it also includes more of the low-level, step-by-step details than some of the more generic references.&lt;/P&gt;

&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Thu, 23 Oct 2014 17:50:14 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Archive/mpi-program/m-p/1033332#M42939</guid>
      <dc:creator>McCalpinJohn</dc:creator>
      <dc:date>2014-10-23T17:50:14Z</dc:date>
    </item>
    <item>
      <title>John,</title>
      <link>https://community.intel.com/t5/Software-Archive/mpi-program/m-p/1033333#M42940</link>
      <description>&lt;P&gt;John,&lt;/P&gt;

&lt;P&gt;Thanks for the reference.&lt;/P&gt;

&lt;P&gt;Regards&lt;BR /&gt;
	--&lt;BR /&gt;
	Taylor&lt;BR /&gt;
	&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Thu, 23 Oct 2014 17:57:26 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Archive/mpi-program/m-p/1033333#M42940</guid>
      <dc:creator>TaylorIoTKidd</dc:creator>
      <dc:date>2014-10-23T17:57:26Z</dc:date>
    </item>
    <item>
      <title>I see in the reference John</title>
      <link>https://community.intel.com/t5/Software-Archive/mpi-program/m-p/1033334#M42941</link>
      <description>&lt;P&gt;I see in the reference John provided a discussion of the case of 16 single thread MPI ranks on host (presumably dual 8-core CPU) and 4 ranks of 30 threads on coprocessor.&amp;nbsp; This is a useful example beyond what has been accepted for posting on IDZ, even if it's relatively unambitious in terms of accelerating performance vs. host alone.&amp;nbsp; It's a good starting point; some jobs ought to scale up to 6 ranks of 30 threads each on coprocessor (depending on number of cores available).&amp;nbsp;&lt;/P&gt;

&lt;P&gt;The MPI pinning settings ought to reserve a group of cores for each rank and distribute the threads evenly across them.&lt;/P&gt;</description>
      <pubDate>Thu, 23 Oct 2014 21:51:26 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Archive/mpi-program/m-p/1033334#M42941</guid>
      <dc:creator>TimP</dc:creator>
      <dc:date>2014-10-23T21:51:26Z</dc:date>
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