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    <title>topic Shouldn't CILK_NWORKERS also in Software Archive</title>
    <link>https://community.intel.com/t5/Software-Archive/Less-performance-on-16-core-than-on-4/m-p/1038064#M44890</link>
    <description>&lt;P&gt;Shouldn't CILK_NWORKERS also be set for such a purpose?&lt;/P&gt;

&lt;P&gt;As my 12-core box is a Westmere dual (HT disabled), to run on 8 cores, with Cilk(tm) Plus using data initialized under OpenMP,&amp;nbsp; I use:&lt;/P&gt;

&lt;P&gt;&amp;nbsp;&lt;/P&gt;

&lt;P&gt;export KMP_AFFINITY="proclist=[1,3,4,5,7,9,10,11],explicit"&amp;nbsp;&amp;nbsp;&amp;nbsp; (effectively setting OMP_NUM_THREADS=8)&lt;/P&gt;

&lt;P&gt;export CILK_NWORKERS=8&lt;/P&gt;

&lt;P&gt;taskset -c 1,3,4,5,7,9,10,11 ./a.out&lt;/P&gt;

&lt;P&gt;&amp;nbsp;&lt;/P&gt;

&lt;P&gt;Hoping to set up so as to use a single core on each of the 4 cache links per CPU,&lt;/P&gt;

&lt;P&gt;and I get the whole expected range of scaling characteristics, some cases running 50% faster with 12 workers than with 8, one 60% faster on 8 cores than on 12.&amp;nbsp; I don't see an obvious way to predict which cases are of one characteristic or another,&amp;nbsp; Due to the 4 cache paths per CPU, it's not entirely a surprise to see some cases max out at 8 workers (possibly sooner when not carefully distributed).&lt;/P&gt;

&lt;P&gt;Even with the verbose option set, it's not clear how taskset is affecting KMP_AFFINITY, but the assumption that taskset doesn't influence that but does (as you found) limit cilkrts seems to work out.&lt;/P&gt;

&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
    <pubDate>Sat, 19 Jul 2014 15:29:00 GMT</pubDate>
    <dc:creator>TimP</dc:creator>
    <dc:date>2014-07-19T15:29:00Z</dc:date>
    <item>
      <title>Less performance on 16 core than on 4 ?!</title>
      <link>https://community.intel.com/t5/Software-Archive/Less-performance-on-16-core-than-on-4/m-p/1038062#M44888</link>
      <description>&lt;P&gt;Hi there,&lt;/P&gt;

&lt;P&gt;I evaluated my cilk application using "taskset -c 0-(x-1) MYPROGRAM) to analyze scaling behavior.&lt;/P&gt;

&lt;P&gt;&amp;nbsp;&lt;/P&gt;

&lt;P&gt;I was very suprised to see, that the performances increases up to a number of cores but decreases afterwards.&lt;BR /&gt;
	&lt;BR /&gt;
	for 2 Cores, I gain a speedup of 1,85. for 4, I gain 3.15. for 8 4.34 - but with 12 cores the performance drops down&lt;BR /&gt;
	to a speedup close to the speedup gained by 2 cores (1.99).&lt;BR /&gt;
	16 cores performe slightly better (2.11)&lt;/P&gt;

&lt;P&gt;How is such an behaviour possible? either an idle thread can steal work or it cant?! - or may the working packets be too coarse grained and the stealing overhead destroys the performance with too many cores in use?!&lt;/P&gt;</description>
      <pubDate>Wed, 11 Jun 2014 12:23:14 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Archive/Less-performance-on-16-core-than-on-4/m-p/1038062#M44888</guid>
      <dc:creator>sdfsadfasdf_s_</dc:creator>
      <dc:date>2014-06-11T12:23:14Z</dc:date>
    </item>
    <item>
      <title>Can you post your example, or</title>
      <link>https://community.intel.com/t5/Software-Archive/Less-performance-on-16-core-than-on-4/m-p/1038063#M44889</link>
      <description>&lt;P&gt;Can you post your example, or an example with similar behavior? &amp;nbsp;Does your machine have a single socket (processor chip) or multiple sockets? &amp;nbsp;Some ways the behavior can happen:&lt;/P&gt;

&lt;UL&gt;
	&lt;LI&gt;As you note, work chunks might be too coarse, and so some threads starve and just run interference trying to steal. &amp;nbsp;&lt;/LI&gt;
	&lt;LI&gt;The communication cost of stealing work might exceed the gains from parallelism. &amp;nbsp;For example, short back-to-back cilk_for loops with high bandwidth/compute ratios are sometimes slowed down by random work-stealing.&lt;/LI&gt;
	&lt;LI&gt;A thread calls a package that is internally multithreaded, thus causing oversubscription.&lt;/LI&gt;
&lt;/UL&gt;</description>
      <pubDate>Tue, 15 Jul 2014 18:40:32 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Archive/Less-performance-on-16-core-than-on-4/m-p/1038063#M44889</guid>
      <dc:creator>ARCH_R_Intel</dc:creator>
      <dc:date>2014-07-15T18:40:32Z</dc:date>
    </item>
    <item>
      <title>Shouldn't CILK_NWORKERS also</title>
      <link>https://community.intel.com/t5/Software-Archive/Less-performance-on-16-core-than-on-4/m-p/1038064#M44890</link>
      <description>&lt;P&gt;Shouldn't CILK_NWORKERS also be set for such a purpose?&lt;/P&gt;

&lt;P&gt;As my 12-core box is a Westmere dual (HT disabled), to run on 8 cores, with Cilk(tm) Plus using data initialized under OpenMP,&amp;nbsp; I use:&lt;/P&gt;

&lt;P&gt;&amp;nbsp;&lt;/P&gt;

&lt;P&gt;export KMP_AFFINITY="proclist=[1,3,4,5,7,9,10,11],explicit"&amp;nbsp;&amp;nbsp;&amp;nbsp; (effectively setting OMP_NUM_THREADS=8)&lt;/P&gt;

&lt;P&gt;export CILK_NWORKERS=8&lt;/P&gt;

&lt;P&gt;taskset -c 1,3,4,5,7,9,10,11 ./a.out&lt;/P&gt;

&lt;P&gt;&amp;nbsp;&lt;/P&gt;

&lt;P&gt;Hoping to set up so as to use a single core on each of the 4 cache links per CPU,&lt;/P&gt;

&lt;P&gt;and I get the whole expected range of scaling characteristics, some cases running 50% faster with 12 workers than with 8, one 60% faster on 8 cores than on 12.&amp;nbsp; I don't see an obvious way to predict which cases are of one characteristic or another,&amp;nbsp; Due to the 4 cache paths per CPU, it's not entirely a surprise to see some cases max out at 8 workers (possibly sooner when not carefully distributed).&lt;/P&gt;

&lt;P&gt;Even with the verbose option set, it's not clear how taskset is affecting KMP_AFFINITY, but the assumption that taskset doesn't influence that but does (as you found) limit cilkrts seems to work out.&lt;/P&gt;

&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Sat, 19 Jul 2014 15:29:00 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Archive/Less-performance-on-16-core-than-on-4/m-p/1038064#M44890</guid>
      <dc:creator>TimP</dc:creator>
      <dc:date>2014-07-19T15:29:00Z</dc:date>
    </item>
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