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    <title>topic vmx guest debug? in Software Archive</title>
    <link>https://community.intel.com/t5/Software-Archive/vmx-guest-debug/m-p/772185#M4796</link>
    <description>Aftersuccessfully launching a guest, the code does not stop in my guest entry function at "INT 3", function that I supplied into the GUEST RIP field of the VMCS. Does anyone have an idea why this is happening?&lt;DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;Here is a VMCS dump on my Intel Core2 CPU 6300 @1.86Ghz with Windows 7 x64:&lt;DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;(Some of the fields here are not supported by the processor, although i've printed them out as well.&lt;/DIV&gt;&lt;DIV&gt;The guest shares resources with the host for now. )&lt;/DIV&gt;&lt;DIV&gt;&lt;DIV id="_mcePaste"&gt;*** Host State ***&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;HOST_CR0: 0x80050031&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;HOST_CR3: 0x187000&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;HOST_CR4: 0x26f8&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;HOST_RSP: 0xfffffa800420ef50&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;HOST_RIP: 0xfffff8800485e749&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;HOST_CS_SELECTOR: 0x10&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;HOST_DS_SELECTOR: 0x28&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;HOST_SS_SELECTOR: 0x18&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;HOST_ES_SELECTOR: 0x28&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;HOST_FS_SELECTOR: 0x50&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;HOST_GS_SELECTOR: 0x28&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;HOST_TR_SELECTOR: 0x40&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;HOST_FS_BASE: 0xfffffffffffdf000&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;HOST_GS_BASE: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;HOST_TR_BASE: 0xb96080&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;HOST_GDTR_BASE: 0xfffff80000b95000&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;HOST_IDTR_BASE: 0xfffff80000b95080&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;HOST_SYSENTER_CS: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;HOST_SYSENTER_ESP: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;HOST_SYSENTER_EIP: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;HOST_PERF_GLOBAL_CTRL: 0xfffff88002322b78 // not supported&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;HOST_PAT: 0xfffff88002322b78// not supported&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;HOST_EFER: 0xfffff88002322b78// not supported&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;*** Guest Register State ***&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_CR0: 0x80050031&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_CR3: 0x187000&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_CR4: 0x26f8&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_RSP: 0xfffff88002322b90&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_RIP: 0xfffff8800485e734&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_DR7: 0x400&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_RFLAGS 0x246&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_CS_SELECTOR: 0x10&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_DS_SELECTOR: 0x2b&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_SS_SELECTOR: 0x18&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_ES_SELECTOR: 0x2b&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_FS_SELECTOR: 0x53&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_GS_SELECTOR: 0x2b&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_LDTR_SELECTOR: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_TR_SELECTOR: 0x40&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_CS_BASE: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_DS_BASE: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_SS_BASE: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_ES_BASE: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_FS_BASE: 0xfffffffffffdf000&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_GS_BASE: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_GDTR_BASE: 0xfffff80000b95000&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_LDTR_BASE: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_IDTR_BASE: 0xfffff80000b95080&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_TR_BASE: 0xb96080&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_CS_LIMIT: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_DS_LIMIT: 0xffffffff&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_SS_LIMIT: 0xffffffff&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_ES_LIMIT: 0xffffffff&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_FS_LIMIT: 0x3c00&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_GS_LIMIT: 0xffffffff&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_GDTR_LIMIT: 0x7f&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_LDTR_LIMIT: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_IDTR_LIMIT: 0xfff&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_TR_LIMIT: 0x67&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_CS_AR_BYTES: 0x209b&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_DS_AR_BYTES: 0xcff3&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_SS_AR_BYTES: 0xcf93&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_ES_AR_BYTES: 0xcff3&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_FS_AR_BYTES: 0x40f3&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_GS_AR_BYTES: 0xcff3&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_LDTR_AR_BYTES: 0x10000&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_TR_AR_BYTES: 0x8b&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_IA32_DEBUGCTL: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_SYSENTER_CS: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_SYSENTER_ESP: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_SYSENTER_EIP: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_PERF_GLOBAL_CTRL: 0xfffff88002322b78// not supported&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_PAT: 0xfffff88002322b78// not supported&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_EFER: 0xfffff88002322b78// not supported&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_SMBASE: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;*** Guest Non-Register State ***&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_ACTIVITY_STATE: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_INTERRUPTIBILITY_INFO: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_PENDING_DBG_EXCEPTIONS: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;VMCS_LINK_POINTER: 0xffffffff&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;VMX_PREEMPTION_TIMER_VALUE: 0x2322b78&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_PDPTR0: 0xfffff88002322b78&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_PDPTR1: 0xfffff88002322b78&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_PDPTR2: 0xfffff88002322b78&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_PDPTR3: 0xfffff88002322b78&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;*** VM-EXECUTION CONTROL FIELDS ***&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;CPU_BASED_VM_EXEC_CONTROL: 0x401e172&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;SECONDARY_VM_EXEC_CONTROL: 0x2322b78&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;* Exception Bitmap *&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;EXCEPTION_BITMAP: 0xffffffff&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;PAGE_FAULT_ERROR_CODE_MASK: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;PAGE_FAULT_ERROR_CODE_MATCH: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;* I/O-Bitmap Addresses *&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;IO_BITMAP_A: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;IO_BITMAP_B: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;* Time-Stamp Counter Offset *&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;TSC_OFFSET: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;* Guest/Host Masks and Read Shadows for CR0 and CR4 *&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;CR0_GUEST_HOST_MASK: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;CR4_GUEST_HOST_MASK: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;CR0_READ_SHADOW: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;CR4_READ_SHADOW: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;* CR3-Target Controls *&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;CR3_TARGET_VALUE0: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;CR3_TARGET_VALUE1: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;CR3_TARGET_VALUE2: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;CR3_TARGET_VALUE3: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;CR3_TARGET_COUNT: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;* Controls for APIC Accesses *&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;APIC_ACCESS_ADDR: 0xfffff88002322b78&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;VIRTUAL_APIC_PAGE_ADDR: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;TPR_THRESHOLD: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;* MSR-Bitmap Address *&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;MSR_BITMAP: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;* Extended-Page-Table Pointer *&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;EPT_POINTER: 0xfffff88002322b78&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;* Virtual-Processor Identifier (VPID) *&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;VIRTUAL_PROCESSOR_ID: 0x2322b78&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;* Controls for PAUSE-Loop Exiting *&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;PLE_GAP: 0x2322b78&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;PLE_WINDOW: 0x2322b78&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;*** VM-Exit Controls ***&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;VM_EXIT_CONTROLS: 0x36fff&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;VM_EXIT_MSR_STORE_COUNT: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;VM_EXIT_MSR_STORE_ADDR: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;VM_EXIT_MSR_LOAD_COUNT: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;VM_EXIT_MSR_LOAD_ADDR: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;*** VM-Entry Controls ***&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;VM_ENTRY_CONTROLS: 0x13ff&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;VM_ENTRY_MSR_LOAD_COUNT: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;VM_ENTRY_MSR_LOAD_ADDR: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;VM_ENTRY_INTR_INFO: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;VM_ENTRY_EXCEPTION_ERROR_CODE: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;VM_ENTRY_INSTRUCTION_LEN: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;*** VM-Exit Information ***&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;VM_EXIT_REASON: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;EXIT_QUALIFICATION: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_LINEAR_ADDRESS: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_PHYSICAL_ADDRESS: 0xfffff88002322b78&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;* Information for VM-Exits Due to Vectored Events *&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;VM_EXIT_INTR_INFO: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;VM_EXIT_INTR_ERROR_CODE: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;* Information for VM-Exits That Occur During Event Delivery *&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;IDT_VECTORING_INFO: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;IDT_VECTORING_ERROR_CODE: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;* Information for VM-Exits Due to Instruction Execution *&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;VM_EXIT_INSTRUCTION_LEN: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;VMX_INSTRUCTION_INFO: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;IO_RCX: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;IO_RSI: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;IO_RDI: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;IO_RIP: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;* VM-Instruction Error Field *&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;VM_INSTRUCTION_ERROR: 0xc&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;***************************************************&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;Thankyou.&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;---------------------------------&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;&lt;A href="http://www.scs.ubbcluj.ro/~tjie0910"&gt;Learn to play the piano: www.scs.ubbcluj.ro/~tjie0910&lt;/A&gt;&lt;/DIV&gt;</description>
    <pubDate>Fri, 03 Dec 2010 10:22:23 GMT</pubDate>
    <dc:creator>blue_dot</dc:creator>
    <dc:date>2010-12-03T10:22:23Z</dc:date>
    <item>
      <title>vmx guest debug?</title>
      <link>https://community.intel.com/t5/Software-Archive/vmx-guest-debug/m-p/772185#M4796</link>
      <description>Aftersuccessfully launching a guest, the code does not stop in my guest entry function at "INT 3", function that I supplied into the GUEST RIP field of the VMCS. Does anyone have an idea why this is happening?&lt;DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;Here is a VMCS dump on my Intel Core2 CPU 6300 @1.86Ghz with Windows 7 x64:&lt;DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;(Some of the fields here are not supported by the processor, although i've printed them out as well.&lt;/DIV&gt;&lt;DIV&gt;The guest shares resources with the host for now. )&lt;/DIV&gt;&lt;DIV&gt;&lt;DIV id="_mcePaste"&gt;*** Host State ***&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;HOST_CR0: 0x80050031&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;HOST_CR3: 0x187000&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;HOST_CR4: 0x26f8&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;HOST_RSP: 0xfffffa800420ef50&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;HOST_RIP: 0xfffff8800485e749&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;HOST_CS_SELECTOR: 0x10&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;HOST_DS_SELECTOR: 0x28&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;HOST_SS_SELECTOR: 0x18&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;HOST_ES_SELECTOR: 0x28&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;HOST_FS_SELECTOR: 0x50&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;HOST_GS_SELECTOR: 0x28&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;HOST_TR_SELECTOR: 0x40&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;HOST_FS_BASE: 0xfffffffffffdf000&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;HOST_GS_BASE: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;HOST_TR_BASE: 0xb96080&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;HOST_GDTR_BASE: 0xfffff80000b95000&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;HOST_IDTR_BASE: 0xfffff80000b95080&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;HOST_SYSENTER_CS: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;HOST_SYSENTER_ESP: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;HOST_SYSENTER_EIP: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;HOST_PERF_GLOBAL_CTRL: 0xfffff88002322b78 // not supported&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;HOST_PAT: 0xfffff88002322b78// not supported&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;HOST_EFER: 0xfffff88002322b78// not supported&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;*** Guest Register State ***&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_CR0: 0x80050031&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_CR3: 0x187000&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_CR4: 0x26f8&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_RSP: 0xfffff88002322b90&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_RIP: 0xfffff8800485e734&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_DR7: 0x400&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_RFLAGS 0x246&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_CS_SELECTOR: 0x10&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_DS_SELECTOR: 0x2b&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_SS_SELECTOR: 0x18&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_ES_SELECTOR: 0x2b&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_FS_SELECTOR: 0x53&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_GS_SELECTOR: 0x2b&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_LDTR_SELECTOR: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_TR_SELECTOR: 0x40&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_CS_BASE: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_DS_BASE: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_SS_BASE: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_ES_BASE: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_FS_BASE: 0xfffffffffffdf000&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_GS_BASE: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_GDTR_BASE: 0xfffff80000b95000&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_LDTR_BASE: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_IDTR_BASE: 0xfffff80000b95080&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_TR_BASE: 0xb96080&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_CS_LIMIT: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_DS_LIMIT: 0xffffffff&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_SS_LIMIT: 0xffffffff&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_ES_LIMIT: 0xffffffff&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_FS_LIMIT: 0x3c00&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_GS_LIMIT: 0xffffffff&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_GDTR_LIMIT: 0x7f&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_LDTR_LIMIT: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_IDTR_LIMIT: 0xfff&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_TR_LIMIT: 0x67&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_CS_AR_BYTES: 0x209b&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_DS_AR_BYTES: 0xcff3&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_SS_AR_BYTES: 0xcf93&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_ES_AR_BYTES: 0xcff3&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_FS_AR_BYTES: 0x40f3&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_GS_AR_BYTES: 0xcff3&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_LDTR_AR_BYTES: 0x10000&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_TR_AR_BYTES: 0x8b&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_IA32_DEBUGCTL: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_SYSENTER_CS: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_SYSENTER_ESP: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_SYSENTER_EIP: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_PERF_GLOBAL_CTRL: 0xfffff88002322b78// not supported&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_PAT: 0xfffff88002322b78// not supported&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_EFER: 0xfffff88002322b78// not supported&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_SMBASE: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;*** Guest Non-Register State ***&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_ACTIVITY_STATE: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_INTERRUPTIBILITY_INFO: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_PENDING_DBG_EXCEPTIONS: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;VMCS_LINK_POINTER: 0xffffffff&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;VMX_PREEMPTION_TIMER_VALUE: 0x2322b78&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_PDPTR0: 0xfffff88002322b78&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_PDPTR1: 0xfffff88002322b78&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_PDPTR2: 0xfffff88002322b78&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_PDPTR3: 0xfffff88002322b78&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;*** VM-EXECUTION CONTROL FIELDS ***&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;CPU_BASED_VM_EXEC_CONTROL: 0x401e172&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;SECONDARY_VM_EXEC_CONTROL: 0x2322b78&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;* Exception Bitmap *&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;EXCEPTION_BITMAP: 0xffffffff&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;PAGE_FAULT_ERROR_CODE_MASK: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;PAGE_FAULT_ERROR_CODE_MATCH: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;* I/O-Bitmap Addresses *&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;IO_BITMAP_A: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;IO_BITMAP_B: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;* Time-Stamp Counter Offset *&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;TSC_OFFSET: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;* Guest/Host Masks and Read Shadows for CR0 and CR4 *&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;CR0_GUEST_HOST_MASK: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;CR4_GUEST_HOST_MASK: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;CR0_READ_SHADOW: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;CR4_READ_SHADOW: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;* CR3-Target Controls *&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;CR3_TARGET_VALUE0: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;CR3_TARGET_VALUE1: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;CR3_TARGET_VALUE2: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;CR3_TARGET_VALUE3: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;CR3_TARGET_COUNT: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;* Controls for APIC Accesses *&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;APIC_ACCESS_ADDR: 0xfffff88002322b78&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;VIRTUAL_APIC_PAGE_ADDR: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;TPR_THRESHOLD: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;* MSR-Bitmap Address *&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;MSR_BITMAP: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;* Extended-Page-Table Pointer *&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;EPT_POINTER: 0xfffff88002322b78&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;* Virtual-Processor Identifier (VPID) *&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;VIRTUAL_PROCESSOR_ID: 0x2322b78&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;* Controls for PAUSE-Loop Exiting *&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;PLE_GAP: 0x2322b78&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;PLE_WINDOW: 0x2322b78&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;*** VM-Exit Controls ***&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;VM_EXIT_CONTROLS: 0x36fff&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;VM_EXIT_MSR_STORE_COUNT: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;VM_EXIT_MSR_STORE_ADDR: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;VM_EXIT_MSR_LOAD_COUNT: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;VM_EXIT_MSR_LOAD_ADDR: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;*** VM-Entry Controls ***&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;VM_ENTRY_CONTROLS: 0x13ff&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;VM_ENTRY_MSR_LOAD_COUNT: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;VM_ENTRY_MSR_LOAD_ADDR: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;VM_ENTRY_INTR_INFO: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;VM_ENTRY_EXCEPTION_ERROR_CODE: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;VM_ENTRY_INSTRUCTION_LEN: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;*** VM-Exit Information ***&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;VM_EXIT_REASON: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;EXIT_QUALIFICATION: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_LINEAR_ADDRESS: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;GUEST_PHYSICAL_ADDRESS: 0xfffff88002322b78&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;* Information for VM-Exits Due to Vectored Events *&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;VM_EXIT_INTR_INFO: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;VM_EXIT_INTR_ERROR_CODE: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;* Information for VM-Exits That Occur During Event Delivery *&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;IDT_VECTORING_INFO: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;IDT_VECTORING_ERROR_CODE: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;* Information for VM-Exits Due to Instruction Execution *&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;VM_EXIT_INSTRUCTION_LEN: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;VMX_INSTRUCTION_INFO: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;IO_RCX: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;IO_RSI: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;IO_RDI: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;IO_RIP: 0x0&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;* VM-Instruction Error Field *&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;VM_INSTRUCTION_ERROR: 0xc&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;***************************************************&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;Thankyou.&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;---------------------------------&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;&lt;A href="http://www.scs.ubbcluj.ro/~tjie0910"&gt;Learn to play the piano: www.scs.ubbcluj.ro/~tjie0910&lt;/A&gt;&lt;/DIV&gt;</description>
      <pubDate>Fri, 03 Dec 2010 10:22:23 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Archive/vmx-guest-debug/m-p/772185#M4796</guid>
      <dc:creator>blue_dot</dc:creator>
      <dc:date>2010-12-03T10:22:23Z</dc:date>
    </item>
    <item>
      <title>vmx guest debug?</title>
      <link>https://community.intel.com/t5/Software-Archive/vmx-guest-debug/m-p/772186#M4797</link>
      <description>&lt;P&gt;Ijust received a brief comment from an engineer as follows:&lt;BR /&gt;&lt;BR /&gt;"The userneeds to identify whether the guestVM exits to the hypervisor due to int 3. Maybe they can try to use the monitor trap flag.It is enabled for Xen, but few people seem to use it."&lt;BR /&gt;&lt;BR /&gt;An earlier comment from the same person:&lt;BR /&gt;&lt;BR /&gt;"I noticed the guest exception map is 0xffffffff whichmeans that the userwants the guest VM toexit to the hypervisor on all kinds of exceptions. Hence, theywill get more VM exits than perhaps theyexpect. I understand they are looking for "int 3" VM exits."&lt;BR /&gt;&lt;BR /&gt;David Ott&lt;/P&gt;</description>
      <pubDate>Thu, 16 Dec 2010 23:17:31 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Archive/vmx-guest-debug/m-p/772186#M4797</guid>
      <dc:creator>David_O_Intel1</dc:creator>
      <dc:date>2010-12-16T23:17:31Z</dc:date>
    </item>
  </channel>
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