<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic MSR-Bitmaps in Software Archive</title>
    <link>https://community.intel.com/t5/Software-Archive/MSR-Bitmaps/m-p/772870#M4816</link>
    <description>Having problems with the MSR bitmaps. &lt;BR /&gt;I read the IA32_VMX_PROCBASED_CTLS MSR, set bit 28 and stored it into the vmcs's Primary proc-based VM-execution controls field. &lt;BR /&gt;I then have the following structure in the vmcs header file:&lt;BR /&gt;&lt;BR /&gt;struct MSR_BITMAP&lt;BR /&gt;{&lt;BR /&gt;u64 MSR_READ_LO[128];&lt;BR /&gt;u64 MSR_READ_HI[128];&lt;BR /&gt;u64 MSR_WRITE_LO[128];&lt;BR /&gt;u64 MSR_WRITE_HI[128];&lt;BR /&gt;} __attribute__ (( aligned (4096) ));&lt;BR /&gt;&lt;BR /&gt;and in the vmcs.cI have the following code that should clear all bits in the MSR bitmap pointed to by the MSR_BITMAP address of the vmcs field so that no MSR read or write will cause a VM exit:&lt;BR /&gt;&lt;BR /&gt;struct MSR_BITMAP MSR_BITMAP1;&lt;BR /&gt;&lt;BR /&gt;unsigned long MSR_BITMAP_ADDR = (unsigned long) &amp;amp;MSR_BITMAP1;&lt;BR /&gt;memset(&amp;amp;MSR_BITMAP1, 0, sizeof(MSR_BITMAP1)); //this should clear all bits in the bitmap forcing no MSRs to cause a VM exit&lt;BR /&gt;__vmwrite (MSR_BITMAP_LO, (u32)MSR_BITMAP_ADDR);&lt;BR /&gt;__vmwrite (MSR_BITMAP_HI, (u32)(MSR_BITMAP_ADDR &amp;gt;&amp;gt; 32));&lt;BR /&gt;&lt;BR /&gt;In the VM i have the following code trying to read a MSR:&lt;BR /&gt;&lt;BR /&gt;rdmsrl(MSR_IA32_APIC_BASE_BSE, apic_base);&lt;BR /&gt;&lt;BR /&gt;However when the VM tries to read the MSR I still get a VM-exit due to a MSR exception. How do I correctly setup the MSR bitmap of the VMCS so that I do not get a VM-exit caused by a MSR exception when I try to read a MSR in the VM. (Trying to write to an MSR in the VM causes a triple fault, hopefully solving this will fix that problem as well.)&lt;BR /&gt;Any suggestions?</description>
    <pubDate>Fri, 13 Apr 2012 13:43:32 GMT</pubDate>
    <dc:creator>heinerj</dc:creator>
    <dc:date>2012-04-13T13:43:32Z</dc:date>
    <item>
      <title>MSR-Bitmaps</title>
      <link>https://community.intel.com/t5/Software-Archive/MSR-Bitmaps/m-p/772870#M4816</link>
      <description>Having problems with the MSR bitmaps. &lt;BR /&gt;I read the IA32_VMX_PROCBASED_CTLS MSR, set bit 28 and stored it into the vmcs's Primary proc-based VM-execution controls field. &lt;BR /&gt;I then have the following structure in the vmcs header file:&lt;BR /&gt;&lt;BR /&gt;struct MSR_BITMAP&lt;BR /&gt;{&lt;BR /&gt;u64 MSR_READ_LO[128];&lt;BR /&gt;u64 MSR_READ_HI[128];&lt;BR /&gt;u64 MSR_WRITE_LO[128];&lt;BR /&gt;u64 MSR_WRITE_HI[128];&lt;BR /&gt;} __attribute__ (( aligned (4096) ));&lt;BR /&gt;&lt;BR /&gt;and in the vmcs.cI have the following code that should clear all bits in the MSR bitmap pointed to by the MSR_BITMAP address of the vmcs field so that no MSR read or write will cause a VM exit:&lt;BR /&gt;&lt;BR /&gt;struct MSR_BITMAP MSR_BITMAP1;&lt;BR /&gt;&lt;BR /&gt;unsigned long MSR_BITMAP_ADDR = (unsigned long) &amp;amp;MSR_BITMAP1;&lt;BR /&gt;memset(&amp;amp;MSR_BITMAP1, 0, sizeof(MSR_BITMAP1)); //this should clear all bits in the bitmap forcing no MSRs to cause a VM exit&lt;BR /&gt;__vmwrite (MSR_BITMAP_LO, (u32)MSR_BITMAP_ADDR);&lt;BR /&gt;__vmwrite (MSR_BITMAP_HI, (u32)(MSR_BITMAP_ADDR &amp;gt;&amp;gt; 32));&lt;BR /&gt;&lt;BR /&gt;In the VM i have the following code trying to read a MSR:&lt;BR /&gt;&lt;BR /&gt;rdmsrl(MSR_IA32_APIC_BASE_BSE, apic_base);&lt;BR /&gt;&lt;BR /&gt;However when the VM tries to read the MSR I still get a VM-exit due to a MSR exception. How do I correctly setup the MSR bitmap of the VMCS so that I do not get a VM-exit caused by a MSR exception when I try to read a MSR in the VM. (Trying to write to an MSR in the VM causes a triple fault, hopefully solving this will fix that problem as well.)&lt;BR /&gt;Any suggestions?</description>
      <pubDate>Fri, 13 Apr 2012 13:43:32 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Archive/MSR-Bitmaps/m-p/772870#M4816</guid>
      <dc:creator>heinerj</dc:creator>
      <dc:date>2012-04-13T13:43:32Z</dc:date>
    </item>
    <item>
      <title>MSR-Bitmaps</title>
      <link>https://community.intel.com/t5/Software-Archive/MSR-Bitmaps/m-p/772871#M4817</link>
      <description>Hello,&lt;DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;so if you have correctly set the use of MSR bitmaps in the execution control field maybe your RCX value is not correctly in his range.&lt;/DIV&gt;&lt;DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;What I mean is: if theMSR_READ_LO is in the range [0, 0x1FFF] so RCX (or ECX) value should be in the same range, the same for other kind of bitmaps. This happens because if you execute __rdmsr without a correct value (ie. in the range) in RCX a VM exit occurs.&lt;/DIV&gt;&lt;DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;EITHER if the bit in the "selected (low/high, read/write)" MSR bitmaps corresponding to the RCX value is 1. So the n_bit (with n = rcx_value) should not be 1.&lt;/DIV&gt;&lt;DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;Tell me what about this check, thanks&lt;/DIV&gt;&lt;DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;irp&lt;/DIV&gt;</description>
      <pubDate>Sat, 14 Apr 2012 11:15:55 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Archive/MSR-Bitmaps/m-p/772871#M4817</guid>
      <dc:creator>interruptrequestpack</dc:creator>
      <dc:date>2012-04-14T11:15:55Z</dc:date>
    </item>
    <item>
      <title>MSR-Bitmaps</title>
      <link>https://community.intel.com/t5/Software-Archive/MSR-Bitmaps/m-p/772872#M4818</link>
      <description>Problem was with the privilege level of my CS segment. Was not able to view the MSRs because my privilege level was 3 not 0.</description>
      <pubDate>Mon, 16 Apr 2012 19:04:08 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Archive/MSR-Bitmaps/m-p/772872#M4818</guid>
      <dc:creator>heinerj</dc:creator>
      <dc:date>2012-04-16T19:04:08Z</dc:date>
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  </channel>
</rss>

