https://community.intel.com/t5/Software-Archive/EPT-violation/m-p/819691#M6033 <P>This exit qualification indicates that the EPT violation occurred due to an attempt to fetch an instruction from a guest-physical address that is not present in the EPT page structures.</P><P>Youshould check the guest-physical address reported by the VM exit (VMREAD 2400H in 64-bit mode) and see how it is translated through the EPT paging structures. If the EPT paging structures produce a valid translation for that guest-physical address, youshould notify us.<BR /><BR />David Ott</P> Thu, 02 Jun 2011 22:51:17 GMT David_O_Intel1 2011-06-02T22:51:17Z https://community.intel.com/t5/Software-Archive/EPT-violation/m-p/819690#M6032 Hi,<BR /><BR />The system with 4KB_page EPT and 2MB_page Host page tables works successfully without any failures. However, when it is switched to 4KB-page EPT and 4KB-page host page tables, EPT violation always occurs with exit qualification 0x184 and the guest physical address causing EPT violation points to the guest RIP address. Any ideas for it?<BR /><BR />Does it matter when I build the system with different page size for host page tables? Thu, 19 May 2011 19:08:54 GMT https://community.intel.com/t5/Software-Archive/EPT-violation/m-p/819690#M6032 hxh2160 2011-05-19T19:08:54Z https://community.intel.com/t5/Software-Archive/EPT-violation/m-p/819691#M6033 <P>This exit qualification indicates that the EPT violation occurred due to an attempt to fetch an instruction from a guest-physical address that is not present in the EPT page structures.</P><P>Youshould check the guest-physical address reported by the VM exit (VMREAD 2400H in 64-bit mode) and see how it is translated through the EPT paging structures. If the EPT paging structures produce a valid translation for that guest-physical address, youshould notify us.<BR /><BR />David Ott</P> Thu, 02 Jun 2011 22:51:17 GMT https://community.intel.com/t5/Software-Archive/EPT-violation/m-p/819691#M6033 David_O_Intel1 2011-06-02T22:51:17Z