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    <title>topic A new CPU meant for Virtual Machines in Software Archive</title>
    <link>https://community.intel.com/t5/Software-Archive/A-new-CPU-meant-for-Virtual-Machines/m-p/822271#M6056</link>
    <description>Hi, You can check out the new site for this new processor: &lt;A href="https://www-ssl.intel.com/content/www/us/en/high-performance-computing/high-performance-xeon-phi-coprocessor-brief.html?"&gt;https://www-ssl.intel.com/content/www/us/en/high-performance-computing/high-performance-xeon-phi-coprocessor-brief.html?&lt;/A&gt;&lt;BR /&gt;Regards&lt;BR /&gt;- Thai &lt;BR /&gt;</description>
    <pubDate>Tue, 03 Jul 2012 07:10:18 GMT</pubDate>
    <dc:creator>Quoc-Thai_L_Intel</dc:creator>
    <dc:date>2012-07-03T07:10:18Z</dc:date>
    <item>
      <title>A new CPU meant for Virtual Machines</title>
      <link>https://community.intel.com/t5/Software-Archive/A-new-CPU-meant-for-Virtual-Machines/m-p/822270#M6055</link>
      <description>&lt;DIV&gt;I was reading an article at Tom's Hardware about the new Intel Many Integrated Core (MIC) architecture currently codenamed "Knights Corner".&lt;/DIV&gt;&lt;A href="http://www.tomshardware.com/news/knights-ferry-corner-mic-xeon,11036.html"&gt;http://www.tomshardware.com/news/knights-ferry-corner-mic-xeon,11036.html&lt;/A&gt;&lt;DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;It has32 x86 cores at 1.2GHz, with four threads per core.&lt;/DIV&gt;&lt;DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;If this isn't intended for virtualization I don't know what is.&lt;/DIV&gt;</description>
      <pubDate>Wed, 15 Sep 2010 21:16:19 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Archive/A-new-CPU-meant-for-Virtual-Machines/m-p/822270#M6055</guid>
      <dc:creator>Tw_Burger</dc:creator>
      <dc:date>2010-09-15T21:16:19Z</dc:date>
    </item>
    <item>
      <title>A new CPU meant for Virtual Machines</title>
      <link>https://community.intel.com/t5/Software-Archive/A-new-CPU-meant-for-Virtual-Machines/m-p/822271#M6056</link>
      <description>Hi, You can check out the new site for this new processor: &lt;A href="https://www-ssl.intel.com/content/www/us/en/high-performance-computing/high-performance-xeon-phi-coprocessor-brief.html?"&gt;https://www-ssl.intel.com/content/www/us/en/high-performance-computing/high-performance-xeon-phi-coprocessor-brief.html?&lt;/A&gt;&lt;BR /&gt;Regards&lt;BR /&gt;- Thai &lt;BR /&gt;</description>
      <pubDate>Tue, 03 Jul 2012 07:10:18 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Archive/A-new-CPU-meant-for-Virtual-Machines/m-p/822271#M6056</guid>
      <dc:creator>Quoc-Thai_L_Intel</dc:creator>
      <dc:date>2012-07-03T07:10:18Z</dc:date>
    </item>
    <item>
      <title>A new CPU meant for Virtual Machines</title>
      <link>https://community.intel.com/t5/Software-Archive/A-new-CPU-meant-for-Virtual-Machines/m-p/822272#M6057</link>
      <description>Its not entirely clear if this is a continuation of Labree where if I understood things correctly the individual processors on the die lacked inter-processor cache coherency (requiring external serialization when necissary), or if phi is some sort of evolution of existing multi-core architectures where inter-processor cache coherency is maintained.&lt;DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;I agree its an interesting processor from a virtualization standpoint either way, but its also not clear what instruction sets each core in a phi part supports, so what kind of virtualization software to make it interesting changes quite a bit depending on the answers to the cache coherency and instruction set question. The link Quoc-tahi Le posted didn't seem to contain any actual technical information.&lt;/DIV&gt;</description>
      <pubDate>Tue, 03 Jul 2012 14:41:41 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Archive/A-new-CPU-meant-for-Virtual-Machines/m-p/822272#M6057</guid>
      <dc:creator>Tracy_Camp</dc:creator>
      <dc:date>2012-07-03T14:41:41Z</dc:date>
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