<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic memory addressing(effective address or offset) in 16 bit protected or real mode in Software Archive</title>
    <link>https://community.intel.com/t5/Software-Archive/memory-addressing-effective-address-or-offset-in-16-bit/m-p/836486#M6325</link>
    <description>We know that memory is addressed by a combination of
(Base+Index*Scale+Displacement). If the code is 16 bit protected mode
and addresses a memory location, can we specify 8 bit registers like
AH, BH .....as base or index registers? &lt;BR /&gt;The same question is for a code that is executed in 16 bit real address (or 64 bit mode). &lt;BR /&gt;&lt;BR /&gt;Intel 64 and IA-32 software developer's manual mentions 32 or 64 bit registers in 64 bit mode I think.</description>
    <pubDate>Wed, 21 Apr 2010 03:22:16 GMT</pubDate>
    <dc:creator>logicman112</dc:creator>
    <dc:date>2010-04-21T03:22:16Z</dc:date>
    <item>
      <title>memory addressing(effective address or offset) in 16 bit protected or real mode</title>
      <link>https://community.intel.com/t5/Software-Archive/memory-addressing-effective-address-or-offset-in-16-bit/m-p/836486#M6325</link>
      <description>We know that memory is addressed by a combination of
(Base+Index*Scale+Displacement). If the code is 16 bit protected mode
and addresses a memory location, can we specify 8 bit registers like
AH, BH .....as base or index registers? &lt;BR /&gt;The same question is for a code that is executed in 16 bit real address (or 64 bit mode). &lt;BR /&gt;&lt;BR /&gt;Intel 64 and IA-32 software developer's manual mentions 32 or 64 bit registers in 64 bit mode I think.</description>
      <pubDate>Wed, 21 Apr 2010 03:22:16 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Archive/memory-addressing-effective-address-or-offset-in-16-bit/m-p/836486#M6325</guid>
      <dc:creator>logicman112</dc:creator>
      <dc:date>2010-04-21T03:22:16Z</dc:date>
    </item>
    <item>
      <title>memory addressing(effective address or offset) in 16 bit protec</title>
      <link>https://community.intel.com/t5/Software-Archive/memory-addressing-effective-address-or-offset-in-16-bit/m-p/836487#M6326</link>
      <description>Sounds to me like you're asking if a post 16-bit cpu could operate as iftreating thememory address space as 8-bit. &lt;BR /&gt;I don't think so</description>
      <pubDate>Fri, 23 Apr 2010 14:31:12 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Archive/memory-addressing-effective-address-or-offset-in-16-bit/m-p/836487#M6326</guid>
      <dc:creator>SHIH_K_Intel</dc:creator>
      <dc:date>2010-04-23T14:31:12Z</dc:date>
    </item>
    <item>
      <title>memory addressing(effective address or offset) in 16 bit protec</title>
      <link>https://community.intel.com/t5/Software-Archive/memory-addressing-effective-address-or-offset-in-16-bit/m-p/836488#M6327</link>
      <description>Thank you to answer my question.&lt;BR /&gt;&lt;BR /&gt;My question is how we can write effective address in 16, 32 or 64 bit modes. We know that the following is a valid effective address in 16 bit IA-32 protected:&lt;BR /&gt;[BX+SI]+disp8&lt;BR /&gt;Can we specify: [BH+SI]+disp8 as an address?&lt;BR /&gt;&lt;BR /&gt;Also suppose we write a code for IA-32 protected, the following is a valid effective address:&lt;BR /&gt;[EAX]+disp32&lt;BR /&gt;&lt;BR /&gt;But is , [AX]+disp32 a valid valid effective address? how about [AL]+disp32?&lt;BR /&gt;&lt;BR /&gt;In real mode(16-bit) we have [BX]+disp8 but is "[BL]+disp8" valid?&lt;BR /&gt;&lt;BR /&gt;And my last question is that how you write a valid address in 64 bit mode? &lt;BR /&gt;&lt;BR /&gt;</description>
      <pubDate>Sat, 24 Apr 2010 07:22:18 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Archive/memory-addressing-effective-address-or-offset-in-16-bit/m-p/836488#M6327</guid>
      <dc:creator>logicman112</dc:creator>
      <dc:date>2010-04-24T07:22:18Z</dc:date>
    </item>
    <item>
      <title>memory addressing(effective address or offset) in 16 bit protec</title>
      <link>https://community.intel.com/t5/Software-Archive/memory-addressing-effective-address-or-offset-in-16-bit/m-p/836489#M6328</link>
      <description>"Can you specify [BH+SI]+disp8 as an address?"&lt;BR /&gt;&lt;BR /&gt;No. &lt;BR /&gt;First you cannot mix register of different sizes. In addressing form, the size of register is governed by the ADDRESS_SIZE attribute, if your codelive in16-bit mode, that attribute is 16 bit by default. If you override ADDRESS_SIZE attribute with the 67H prefix, the ADDRESS_SIZE becomes 32-bit. &lt;BR /&gt;&lt;BR /&gt;So, an assembler will reject the syntax if you try, and the hardware will operate in 16/32/64-bit address space, depending on the operatingmode. And ADDRESS_SIZE prefix override onlyapply in 16/32 bit modes.</description>
      <pubDate>Tue, 25 May 2010 20:27:18 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Archive/memory-addressing-effective-address-or-offset-in-16-bit/m-p/836489#M6328</guid>
      <dc:creator>SHIH_K_Intel</dc:creator>
      <dc:date>2010-05-25T20:27:18Z</dc:date>
    </item>
  </channel>
</rss>

