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    <title>topic question on cache eviction in Software Archive</title>
    <link>https://community.intel.com/t5/Software-Archive/question-on-cache-eviction/m-p/1090083#M64987</link>
    <description>&lt;P&gt;&lt;SPAN style="font-size: 1em; line-height: 1.5;"&gt;I'm experimenting on cache eviction in my code using _mm_clevict(), and have the following observations:&lt;/SPAN&gt;&lt;/P&gt;

&lt;P&gt;(1) if data are evicted from L1 alone (&lt;SPAN style="color: rgb(51, 51, 51); font-family: 'Courier New', Courier, monospace; font-size: 13.3333px; line-height: 16px; background-color: rgb(245, 245, 245);"&gt;_MM_HINT_T0&lt;/SPAN&gt;), the code is slowed by ~30%.&lt;/P&gt;

&lt;P&gt;(2) if data are evicted from L2 alone (&lt;SPAN style="color: rgb(51, 51, 51); font-family: 'Courier New', Courier, monospace; font-size: 13.3333px; line-height: 16px; background-color: rgb(245, 245, 245);"&gt;_MM_HINT_T1&lt;/SPAN&gt;), the code is slowed by ~70%.&lt;/P&gt;

&lt;P&gt;(3) if data are evicted from both L1 and L2, the code is still slowed by ~70%.&lt;/P&gt;

&lt;P&gt;I'm confused by (3), as I think some additional loads should miss both L1 and L2 compared to (2), which should cause further latency. A&lt;SPAN style="font-size: 1em; line-height: 1.5;"&gt;ny thoughts? Thanks!&lt;/SPAN&gt;&lt;/P&gt;</description>
    <pubDate>Sun, 17 Jan 2016 03:57:09 GMT</pubDate>
    <dc:creator>King_Crimson</dc:creator>
    <dc:date>2016-01-17T03:57:09Z</dc:date>
    <item>
      <title>question on cache eviction</title>
      <link>https://community.intel.com/t5/Software-Archive/question-on-cache-eviction/m-p/1090083#M64987</link>
      <description>&lt;P&gt;&lt;SPAN style="font-size: 1em; line-height: 1.5;"&gt;I'm experimenting on cache eviction in my code using _mm_clevict(), and have the following observations:&lt;/SPAN&gt;&lt;/P&gt;

&lt;P&gt;(1) if data are evicted from L1 alone (&lt;SPAN style="color: rgb(51, 51, 51); font-family: 'Courier New', Courier, monospace; font-size: 13.3333px; line-height: 16px; background-color: rgb(245, 245, 245);"&gt;_MM_HINT_T0&lt;/SPAN&gt;), the code is slowed by ~30%.&lt;/P&gt;

&lt;P&gt;(2) if data are evicted from L2 alone (&lt;SPAN style="color: rgb(51, 51, 51); font-family: 'Courier New', Courier, monospace; font-size: 13.3333px; line-height: 16px; background-color: rgb(245, 245, 245);"&gt;_MM_HINT_T1&lt;/SPAN&gt;), the code is slowed by ~70%.&lt;/P&gt;

&lt;P&gt;(3) if data are evicted from both L1 and L2, the code is still slowed by ~70%.&lt;/P&gt;

&lt;P&gt;I'm confused by (3), as I think some additional loads should miss both L1 and L2 compared to (2), which should cause further latency. A&lt;SPAN style="font-size: 1em; line-height: 1.5;"&gt;ny thoughts? Thanks!&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Sun, 17 Jan 2016 03:57:09 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Archive/question-on-cache-eviction/m-p/1090083#M64987</guid>
      <dc:creator>King_Crimson</dc:creator>
      <dc:date>2016-01-17T03:57:09Z</dc:date>
    </item>
    <item>
      <title>The caches are inclusive,</title>
      <link>https://community.intel.com/t5/Software-Archive/question-on-cache-eviction/m-p/1090084#M64988</link>
      <description>&lt;P&gt;The caches are &lt;A href="https://en.wikipedia.org/wiki/CPU_cache#Exclusive_versus_inclusive"&gt;inclusive&lt;/A&gt;, therefore eviction from the L2$ implies eviction from the L1$ too. Your &amp;nbsp;last two cases are therefore identical (give or take the extra eviction instructions you execute!)&lt;/P&gt;</description>
      <pubDate>Mon, 18 Jan 2016 09:47:16 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Archive/question-on-cache-eviction/m-p/1090084#M64988</guid>
      <dc:creator>James_C_Intel2</dc:creator>
      <dc:date>2016-01-18T09:47:16Z</dc:date>
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