https://community.intel.com/t5/Software-Archive/Performance-Monitoring-Instruction-cache/m-p/864487#M7870 Hi everybody,<BR />I'm a newbie, and its my first post here, so hope this is the right forum for asking my question (apologize if its wrong forum...)<BR /><BR />I am performing some performance monitoring on my Intel Core 2 Duo E 6550, my goal is to show if when disabling all caches (I-cache, L1 data cahce, L2 shared cache....) the execution time may become more predictable....I know that there are other parameters to take into account, but I decided to start by testing the influence of cache memories....<BR />So, I've read the Intel Architecture Manual, and found out HOW to disable all caches...in breif, for L2 cache I am using a tool called MSRTool which allows me to set bit 9 and 16 in order to turn off the L2 caches. My PMT (Performance Monitoring Tool) is called PFMON (http://perfmon2.sourceforge.net/pfmon_usersguide.html) and it allowed me to check that L2 Data cache was really disabled...and PFMON showed that there were neither L2 data cache misses nor L2 cahce hit anymore.<BR />Well, Now I decided to disable L1 Instruction cache, and Intel Architecture Manual says that this may be done by setting bit 30 of CR0 (Control register 0). I think it really did disable L1 I-cache because my computer started to run slower.<BR />The problem is that when I check it with PFMON, it seems to remain turned on...there is still L1 instruction cache misses and hits.<BR />Anybody knows how this could be possible? I think that I've just turned off one part of the cache, and some other is still working, but I cant explain how?<BR /><BR />thank you for your answer!<BR /><BR />Ouali.<BR /> Wed, 23 Sep 2009 08:10:56 GMT ouali 2009-09-23T08:10:56Z https://community.intel.com/t5/Software-Archive/Performance-Monitoring-Instruction-cache/m-p/864487#M7870 Hi everybody,<BR />I'm a newbie, and its my first post here, so hope this is the right forum for asking my question (apologize if its wrong forum...)<BR /><BR />I am performing some performance monitoring on my Intel Core 2 Duo E 6550, my goal is to show if when disabling all caches (I-cache, L1 data cahce, L2 shared cache....) the execution time may become more predictable....I know that there are other parameters to take into account, but I decided to start by testing the influence of cache memories....<BR />So, I've read the Intel Architecture Manual, and found out HOW to disable all caches...in breif, for L2 cache I am using a tool called MSRTool which allows me to set bit 9 and 16 in order to turn off the L2 caches. My PMT (Performance Monitoring Tool) is called PFMON (http://perfmon2.sourceforge.net/pfmon_usersguide.html) and it allowed me to check that L2 Data cache was really disabled...and PFMON showed that there were neither L2 data cache misses nor L2 cahce hit anymore.<BR />Well, Now I decided to disable L1 Instruction cache, and Intel Architecture Manual says that this may be done by setting bit 30 of CR0 (Control register 0). I think it really did disable L1 I-cache because my computer started to run slower.<BR />The problem is that when I check it with PFMON, it seems to remain turned on...there is still L1 instruction cache misses and hits.<BR />Anybody knows how this could be possible? I think that I've just turned off one part of the cache, and some other is still working, but I cant explain how?<BR /><BR />thank you for your answer!<BR /><BR />Ouali.<BR /> Wed, 23 Sep 2009 08:10:56 GMT https://community.intel.com/t5/Software-Archive/Performance-Monitoring-Instruction-cache/m-p/864487#M7870 ouali 2009-09-23T08:10:56Z