https://community.intel.com/t5/Software-Archive/APL-LPDDR4-Memory-Bit-and-Byte-Lane-swapping/m-p/1128702#M79948 <P>Hi, we are designing a new board with ApolloLake and LPDDR4. We are using the memory bit and byte lane swapping rules (cap.&nbsp;5.4.3.1 of&nbsp;Design Guide&nbsp;Document Number: 557775) and these rules are similar to&nbsp;Apollo Lake Platform MRD (Document Number: 572383).</P><P>How can I set these&nbsp;bit and byte lane swapping rules on Intel Firmware Engine project?</P><P>I search documentation or tool setup, but I don't find info about it.</P><P>Can you help us?</P><P>Thanks a lot</P><P>Roberto</P> Tue, 08 Jan 2019 08:40:23 GMT Grignaffini__Roberto 2019-01-08T08:40:23Z https://community.intel.com/t5/Software-Archive/APL-LPDDR4-Memory-Bit-and-Byte-Lane-swapping/m-p/1128702#M79948 <P>Hi, we are designing a new board with ApolloLake and LPDDR4. We are using the memory bit and byte lane swapping rules (cap.&nbsp;5.4.3.1 of&nbsp;Design Guide&nbsp;Document Number: 557775) and these rules are similar to&nbsp;Apollo Lake Platform MRD (Document Number: 572383).</P><P>How can I set these&nbsp;bit and byte lane swapping rules on Intel Firmware Engine project?</P><P>I search documentation or tool setup, but I don't find info about it.</P><P>Can you help us?</P><P>Thanks a lot</P><P>Roberto</P> Tue, 08 Jan 2019 08:40:23 GMT https://community.intel.com/t5/Software-Archive/APL-LPDDR4-Memory-Bit-and-Byte-Lane-swapping/m-p/1128702#M79948 Grignaffini__Roberto 2019-01-08T08:40:23Z