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    <title>topic Re: Can I make some load ops not polluting cache? in Software Archive</title>
    <link>https://community.intel.com/t5/Software-Archive/Can-I-make-some-load-ops-not-polluting-cache/m-p/866216#M8016</link>
    <description>&lt;P&gt;You are welcome to experiment with hardware prefetch settings to avoid speculative fetching of cache lines. Platforms where this is likely to make a difference often have such options in BIOS setup. &lt;/P&gt;
&lt;P&gt;I'm sure you are aware that large stride arrays simply aren't efficient on cache architectures, and architectures which provide a cache bypass for them have not been successful on the market. It's probably less expensive to buy the largest available cache than to implement cache bypass measures.&lt;/P&gt;</description>
    <pubDate>Tue, 24 Apr 2007 16:02:06 GMT</pubDate>
    <dc:creator>TimP</dc:creator>
    <dc:date>2007-04-24T16:02:06Z</dc:date>
    <item>
      <title>Can I make some load ops not polluting cache?</title>
      <link>https://community.intel.com/t5/Software-Archive/Can-I-make-some-load-ops-not-polluting-cache/m-p/866215#M8015</link>
      <description>&lt;P&gt;I want to make a data copying operation such as B[1 : n : 1] = A[1 : stride*n : stride], because arrayA has neither temporary reuse norspatial reuse, I don't want array Ato pollute cache while loading. Any way to achieve it ? &lt;/P&gt;
&lt;P&gt;I find that store operations have non-polluting cache version in SSE2, but no counterpart about load operations, why ? Any implementation obstacle or other consideration?&lt;/P&gt;
&lt;P&gt;Thanks for help.&lt;/P&gt;</description>
      <pubDate>Tue, 24 Apr 2007 07:58:51 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Archive/Can-I-make-some-load-ops-not-polluting-cache/m-p/866215#M8015</guid>
      <dc:creator>yxyymagic</dc:creator>
      <dc:date>2007-04-24T07:58:51Z</dc:date>
    </item>
    <item>
      <title>Re: Can I make some load ops not polluting cache?</title>
      <link>https://community.intel.com/t5/Software-Archive/Can-I-make-some-load-ops-not-polluting-cache/m-p/866216#M8016</link>
      <description>&lt;P&gt;You are welcome to experiment with hardware prefetch settings to avoid speculative fetching of cache lines. Platforms where this is likely to make a difference often have such options in BIOS setup. &lt;/P&gt;
&lt;P&gt;I'm sure you are aware that large stride arrays simply aren't efficient on cache architectures, and architectures which provide a cache bypass for them have not been successful on the market. It's probably less expensive to buy the largest available cache than to implement cache bypass measures.&lt;/P&gt;</description>
      <pubDate>Tue, 24 Apr 2007 16:02:06 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Archive/Can-I-make-some-load-ops-not-polluting-cache/m-p/866216#M8016</guid>
      <dc:creator>TimP</dc:creator>
      <dc:date>2007-04-24T16:02:06Z</dc:date>
    </item>
    <item>
      <title>Re: Can I make some load ops not polluting cache?</title>
      <link>https://community.intel.com/t5/Software-Archive/Can-I-make-some-load-ops-not-polluting-cache/m-p/866217#M8017</link>
      <description>&lt;P&gt;You will be happy to hear that SSE4.1 available in H2 this year with Penryn CPU has instruction &lt;B&gt;MOVNTDQA&lt;/B&gt; which is essentially a streaming load operation. It bypasses the cache and uses streaming buffers for loading data.&lt;/P&gt;
&lt;P&gt;Unfortunately, initial implementation of MOVNTDQA will act upon USWC (uncacheable, write combining) memory because it is meant to improve MMIO operations. Future implementations may also work on WB (writeback) memory type enabling you to do exactly what you want here.&lt;/P&gt;
&lt;P&gt;As of now it is simply impossible but with some patience...&lt;/P&gt;</description>
      <pubDate>Fri, 11 May 2007 03:21:07 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Archive/Can-I-make-some-load-ops-not-polluting-cache/m-p/866217#M8017</guid>
      <dc:creator>levicki</dc:creator>
      <dc:date>2007-05-11T03:21:07Z</dc:date>
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