https://community.intel.com/t5/Intel-Software-Guard-Extensions/Intel-SGX-TCS-fields/m-p/1097076#M1012 The current SGX Programming Reference (v. 329298-002, linked from <A href="https://software.intel.com/en-us/isa-extensions/intel-sgx" target="_blank">https://software.intel.com/en-us/isa-extensions/intel-sgx</A> ) describes them as follows in Table 2-5 (part of Section 2.8: Thread Control Structure): OFSBASGX: When added to the base address of the enclave, produces the base address FS segment inside the enclave. Must be page aligned. OGSBASGX: When added to the base address of the enclave, produces the base address GS segment inside the enclave. Must be page aligned. FSLIMIT: Size to become the new FS limit in 32-bit mode GSLIMIT: Size to become the new GS limit in 32-bit mode More information on "Segment Registers" can be found in Volume 1 of Intel® 64 and IA-32 Architectures Software Developer’s Manual ( <A href="http://www.intel.com/content/www/us/en/processors/architectures-software-developer-manuals.html" target="_blank">http://www.intel.com/content/www/us/en/processors/architectures-software-developer-manuals.html</A> ) Mon, 14 Mar 2016 19:59:35 GMT Francisco_C_Intel 2016-03-14T19:59:35Z https://community.intel.com/t5/Intel-Software-Guard-Extensions/Intel-SGX-TCS-fields/m-p/1097075#M1011 <P>What are the use of fields called OFSBASGX, OGSBASGX, FSLIMIT and GSLIMIT in TCS?</P> Thu, 03 Mar 2016 14:06:37 GMT https://community.intel.com/t5/Intel-Software-Guard-Extensions/Intel-SGX-TCS-fields/m-p/1097075#M1011 gu_j_1 2016-03-03T14:06:37Z https://community.intel.com/t5/Intel-Software-Guard-Extensions/Intel-SGX-TCS-fields/m-p/1097076#M1012 The current SGX Programming Reference (v. 329298-002, linked from <A href="https://software.intel.com/en-us/isa-extensions/intel-sgx" target="_blank">https://software.intel.com/en-us/isa-extensions/intel-sgx</A> ) describes them as follows in Table 2-5 (part of Section 2.8: Thread Control Structure): OFSBASGX: When added to the base address of the enclave, produces the base address FS segment inside the enclave. Must be page aligned. OGSBASGX: When added to the base address of the enclave, produces the base address GS segment inside the enclave. Must be page aligned. FSLIMIT: Size to become the new FS limit in 32-bit mode GSLIMIT: Size to become the new GS limit in 32-bit mode More information on "Segment Registers" can be found in Volume 1 of Intel® 64 and IA-32 Architectures Software Developer’s Manual ( <A href="http://www.intel.com/content/www/us/en/processors/architectures-software-developer-manuals.html" target="_blank">http://www.intel.com/content/www/us/en/processors/architectures-software-developer-manuals.html</A> ) Mon, 14 Mar 2016 19:59:35 GMT https://community.intel.com/t5/Intel-Software-Guard-Extensions/Intel-SGX-TCS-fields/m-p/1097076#M1012 Francisco_C_Intel 2016-03-14T19:59:35Z