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<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
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    <title>topic Hi all, in Intel® Software Guard Extensions (Intel® SGX)</title>
    <link>https://community.intel.com/t5/Intel-Software-Guard-Extensions/Intel-SGX-instructions-nowhere-to-be-found/m-p/1099953#M1077</link>
    <description>&lt;P&gt;Hi all,&lt;/P&gt;

&lt;P&gt;In addition, I find in the disassembly of enclave.so, there exist enclu[ecreate], which is rax = 0x0 and enclu. That seems to contradict with encls[ecreate]. I wonder why is that? Can someone help me out?&lt;/P&gt;

&lt;P&gt;&lt;SPAN style="font-size: 1em;"&gt;Also, for the original post, you may want to use GNU assembler 2.25.1 or above, GNU assembler 2.24 cannot recognize enclu or encls.&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;

&lt;P&gt;&lt;SPAN style="font-size: 1em;"&gt;Ruide&lt;/SPAN&gt;&lt;/P&gt;</description>
    <pubDate>Thu, 26 Jan 2017 23:21:06 GMT</pubDate>
    <dc:creator>Zhang__Ruide</dc:creator>
    <dc:date>2017-01-26T23:21:06Z</dc:date>
    <item>
      <title>Intel SGX instructions nowhere to be found</title>
      <link>https://community.intel.com/t5/Intel-Software-Guard-Extensions/Intel-SGX-instructions-nowhere-to-be-found/m-p/1099949#M1073</link>
      <description>&lt;P&gt;To gain a deeper understanding of what's going on behind the scenes I am currently looking into the Linux Intel SGX SDK source and also compiled code of applications and enclaves.&lt;/P&gt;

&lt;P&gt;My problem is that I cannot find the instructions ENCLS and ENCLU - neither in the source nor in the binaries (with binaries I mean the application as well as the enclave).&lt;/P&gt;

&lt;P&gt;My questions:&lt;/P&gt;

&lt;P&gt;1. At what point are these instructions executed and how can I find their locations?&lt;/P&gt;

&lt;P&gt;2. Do current tools like objdump recognize these instructions?&lt;/P&gt;</description>
      <pubDate>Tue, 29 Nov 2016 14:52:30 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Software-Guard-Extensions/Intel-SGX-instructions-nowhere-to-be-found/m-p/1099949#M1073</guid>
      <dc:creator>Urs_M_</dc:creator>
      <dc:date>2016-11-29T14:52:30Z</dc:date>
    </item>
    <item>
      <title>Hello,</title>
      <link>https://community.intel.com/t5/Intel-Software-Guard-Extensions/Intel-SGX-instructions-nowhere-to-be-found/m-p/1099950#M1074</link>
      <description>&lt;P&gt;Hello,&lt;/P&gt;

&lt;P&gt;At the linux sdk sources (https://github.com/01org/linux-sgx) look at linux-sgx/psw/urts/linux/enter_enclave.s&lt;/P&gt;

&lt;P&gt;There is a label called "do_eenter" (line 50, in my version which is pretty recent). There you will find:&lt;/P&gt;

&lt;P&gt;&amp;nbsp;&lt;/P&gt;

&lt;BLOCKQUOTE&gt;
	&lt;P&gt;.Ldo_eenter:&lt;BR /&gt;
		&amp;nbsp;&amp;nbsp;&amp;nbsp; mov frame_arg0, %xbx&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; /* tcs addr */&lt;BR /&gt;
		&amp;nbsp;&amp;nbsp;&amp;nbsp; lea_pic .Lasync_exit_pointer, %xcx&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; /* aep addr */&lt;BR /&gt;
		&amp;nbsp;&amp;nbsp;&amp;nbsp; mov $SE_EENTER, %xax&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; /* EENTER leaf */&lt;/P&gt;

	&lt;P&gt;.Leenter_inst:&lt;BR /&gt;
		&amp;nbsp;&amp;nbsp;&amp;nbsp; &lt;STRONG&gt;&lt;U&gt;ENCLU&lt;/U&gt;&lt;/STRONG&gt;&lt;/P&gt;
&lt;/BLOCKQUOTE&gt;

&lt;P&gt;&amp;nbsp;&lt;/P&gt;

&lt;P&gt;I personally like to search for things with grep: "grep ENCLU * -rn".&lt;/P&gt;

&lt;P&gt;&amp;nbsp;&lt;/P&gt;

&lt;P&gt;Ofir&lt;/P&gt;</description>
      <pubDate>Tue, 29 Nov 2016 16:14:44 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Software-Guard-Extensions/Intel-SGX-instructions-nowhere-to-be-found/m-p/1099950#M1074</guid>
      <dc:creator>Ofir_W_</dc:creator>
      <dc:date>2016-11-29T16:14:44Z</dc:date>
    </item>
    <item>
      <title>Well, this is embarassing. I</title>
      <link>https://community.intel.com/t5/Intel-Software-Guard-Extensions/Intel-SGX-instructions-nowhere-to-be-found/m-p/1099951#M1075</link>
      <description>&lt;P&gt;Well, this is embarassing. I actually used grep but messed up the parameters.&lt;/P&gt;

&lt;P&gt;Thank you very much.&lt;/P&gt;</description>
      <pubDate>Tue, 29 Nov 2016 16:20:38 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Software-Guard-Extensions/Intel-SGX-instructions-nowhere-to-be-found/m-p/1099951#M1075</guid>
      <dc:creator>Urs_M_</dc:creator>
      <dc:date>2016-11-29T16:20:38Z</dc:date>
    </item>
    <item>
      <title>Hi all, </title>
      <link>https://community.intel.com/t5/Intel-Software-Guard-Extensions/Intel-SGX-instructions-nowhere-to-be-found/m-p/1099952#M1076</link>
      <description>&lt;P&gt;Hi all,&amp;nbsp;&lt;/P&gt;

&lt;P&gt;Actually you can find ENCLU in the enclave.so if you are using hardware mode.&amp;nbsp;&lt;/P&gt;

&lt;P&gt;But I still cannot find ENCLS. According to the intel programmer reference, encls should be used to create enclave and enclu to enter and exit enclave. So can someone tell me where can i find the code which creates enclave (i.e. ENCLS)?&lt;/P&gt;

&lt;P&gt;&lt;SPAN style="font-size: 1em;"&gt;Thank you!&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;

&lt;P&gt;&lt;SPAN style="font-size: 1em;"&gt;Ruide&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Thu, 26 Jan 2017 22:45:03 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Software-Guard-Extensions/Intel-SGX-instructions-nowhere-to-be-found/m-p/1099952#M1076</guid>
      <dc:creator>Zhang__Ruide</dc:creator>
      <dc:date>2017-01-26T22:45:03Z</dc:date>
    </item>
    <item>
      <title>Hi all,</title>
      <link>https://community.intel.com/t5/Intel-Software-Guard-Extensions/Intel-SGX-instructions-nowhere-to-be-found/m-p/1099953#M1077</link>
      <description>&lt;P&gt;Hi all,&lt;/P&gt;

&lt;P&gt;In addition, I find in the disassembly of enclave.so, there exist enclu[ecreate], which is rax = 0x0 and enclu. That seems to contradict with encls[ecreate]. I wonder why is that? Can someone help me out?&lt;/P&gt;

&lt;P&gt;&lt;SPAN style="font-size: 1em;"&gt;Also, for the original post, you may want to use GNU assembler 2.25.1 or above, GNU assembler 2.24 cannot recognize enclu or encls.&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;

&lt;P&gt;&lt;SPAN style="font-size: 1em;"&gt;Ruide&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Thu, 26 Jan 2017 23:21:06 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Software-Guard-Extensions/Intel-SGX-instructions-nowhere-to-be-found/m-p/1099953#M1077</guid>
      <dc:creator>Zhang__Ruide</dc:creator>
      <dc:date>2017-01-26T23:21:06Z</dc:date>
    </item>
    <item>
      <title>ECREATE is ENCLS with EAX=00.</title>
      <link>https://community.intel.com/t5/Intel-Software-Guard-Extensions/Intel-SGX-instructions-nowhere-to-be-found/m-p/1099954#M1078</link>
      <description>&lt;P&gt;ECREATE is ENCLS with EAX=00.&lt;/P&gt;

&lt;P&gt;EREPORT is ENCLU with EAX=00&lt;/P&gt;

&lt;P&gt;You can find ENCLS instructions in the driver, EENTER and ERESUME in the uRTS, and EEXIT, EGETKEY, and EREPORT inside the enclave.&lt;/P&gt;</description>
      <pubDate>Fri, 27 Jan 2017 12:55:29 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Software-Guard-Extensions/Intel-SGX-instructions-nowhere-to-be-found/m-p/1099954#M1078</guid>
      <dc:creator>Juan_d_Intel</dc:creator>
      <dc:date>2017-01-27T12:55:29Z</dc:date>
    </item>
    <item>
      <title>Quote:Juan del Cuvillo (Intel</title>
      <link>https://community.intel.com/t5/Intel-Software-Guard-Extensions/Intel-SGX-instructions-nowhere-to-be-found/m-p/1099955#M1079</link>
      <description>&lt;P&gt;&lt;/P&gt;&lt;BLOCKQUOTE&gt;Juan del Cuvillo (Intel) wrote:&lt;BR /&gt;&lt;P&gt;&lt;/P&gt;

&lt;P&gt;ECREATE is ENCLS with EAX=00.&lt;/P&gt;

&lt;P&gt;EREPORT is ENCLU with EAX=00&lt;/P&gt;

&lt;P&gt;You can find ENCLS instructions in the driver, EENTER and ERESUME in the uRTS, and EEXIT, EGETKEY, and EREPORT inside the enclave.&lt;/P&gt;

&lt;P&gt;&lt;/P&gt;&lt;/BLOCKQUOTE&gt;&lt;P&gt;&lt;/P&gt;

&lt;P&gt;Hi, I am able to find EENTER, EEXIT, EGETKEY, and EREPORT. However, I cannot find ERESUME leaf functions in the sdk.&lt;/P&gt;

&lt;P&gt;Could you explain how it is used to resume the enclave after a fault?&lt;/P&gt;

&lt;P&gt;Thanks&lt;/P&gt;</description>
      <pubDate>Sun, 24 Sep 2017 15:39:33 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Software-Guard-Extensions/Intel-SGX-instructions-nowhere-to-be-found/m-p/1099955#M1079</guid>
      <dc:creator>yunfeng7854</dc:creator>
      <dc:date>2017-09-24T15:39:33Z</dc:date>
    </item>
    <item>
      <title>I think it's here:</title>
      <link>https://community.intel.com/t5/Intel-Software-Guard-Extensions/Intel-SGX-instructions-nowhere-to-be-found/m-p/1099956#M1080</link>
      <description>&lt;P&gt;I think it's here:&lt;/P&gt;

&lt;P&gt;&lt;A href="https://github.com/01org/linux-sgx/blob/1115c195cd60d5ab2b80c12d07e21663e5aa8030/psw/urts/linux/sig_handler.cpp"&gt;https://github.com/01org/linux-sgx/blob/1115c195cd60d5ab2b80c12d07e21663e5aa8030/psw/urts/linux/sig_handler.cpp&lt;/A&gt;&lt;/P&gt;</description>
      <pubDate>Tue, 26 Sep 2017 18:06:45 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Software-Guard-Extensions/Intel-SGX-instructions-nowhere-to-be-found/m-p/1099956#M1080</guid>
      <dc:creator>Francisco_C_Intel</dc:creator>
      <dc:date>2017-09-26T18:06:45Z</dc:date>
    </item>
    <item>
      <title>Quote:Francisco C. (Intel)</title>
      <link>https://community.intel.com/t5/Intel-Software-Guard-Extensions/Intel-SGX-instructions-nowhere-to-be-found/m-p/1099957#M1081</link>
      <description>&lt;P&gt;&lt;/P&gt;&lt;BLOCKQUOTE&gt;Francisco C. (Intel) wrote:&lt;BR /&gt;&lt;P&gt;&lt;/P&gt;

&lt;P&gt;I think it's here:&lt;/P&gt;

&lt;P&gt;&lt;A href="https://github.com/01org/linux-sgx/blob/1115c195cd60d5ab2b80c12d07e21663e5aa8030/psw/urts/linux/sig_handler.cpp" rel="nofollow"&gt;https://github.com/01org/linux-sgx/blob/1115c195cd60d5ab2b80c12d07e21663e5aa8030/psw/urts/linux/sig_handler.cpp&lt;/A&gt;&lt;/P&gt;

&lt;P&gt;&lt;/P&gt;&lt;/BLOCKQUOTE&gt;&lt;P&gt;&lt;/P&gt;

&lt;P&gt;Thank you for the reply. I used the SDK compiled in DEBUG=1 mode. However&lt;SPAN class="pl-en"&gt; by looking at the &lt;/SPAN&gt;&lt;SPAN class="pl-c1"&gt;SE_TRACE information&lt;/SPAN&gt;, I think the &lt;SPAN class="pl-en"&gt;"sig_handler" function was not triggered after page faults. ("sig_handler" is triggered if there is an exception such as "divided by zero".)&lt;/SPAN&gt;&lt;/P&gt;

&lt;P&gt;&lt;SPAN class="pl-en"&gt;According to the manual, ERESUME should be used by the untrusted code to return to the enclave after a page fault.&lt;/SPAN&gt;&lt;/P&gt;

&lt;P&gt;&lt;SPAN class="pl-en"&gt;I used the grep command to search from the SDK code, and found the only place of ERESUME was here too.&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Wed, 27 Sep 2017 01:03:00 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Software-Guard-Extensions/Intel-SGX-instructions-nowhere-to-be-found/m-p/1099957#M1081</guid>
      <dc:creator>yunfeng7854</dc:creator>
      <dc:date>2017-09-27T01:03:00Z</dc:date>
    </item>
    <item>
      <title>When async exit happens,</title>
      <link>https://community.intel.com/t5/Intel-Software-Guard-Extensions/Intel-SGX-instructions-nowhere-to-be-found/m-p/1099958#M1082</link>
      <description>&lt;P&gt;When async exit happens, processor cook up something called synthetic state, which loads RAX with ERESUME leaf code, and so on.&lt;/P&gt;

&lt;P&gt;So in uRTS we have the trampoline for ERESUME defined at line 110 in this file:https://github.com/01org/linux-sgx/blob/1115c195cd60d5ab2b80c12d07e21663e5aa8030/psw/urts/linux/enter_enclave.S#L110&lt;/P&gt;

&lt;P&gt;See also SDM vol 3, section 39.3&lt;/P&gt;</description>
      <pubDate>Wed, 27 Sep 2017 04:22:23 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Software-Guard-Extensions/Intel-SGX-instructions-nowhere-to-be-found/m-p/1099958#M1082</guid>
      <dc:creator>Haitao_H_Intel</dc:creator>
      <dc:date>2017-09-27T04:22:23Z</dc:date>
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  </channel>
</rss>

