topic Several notes: in Intel® Software Guard Extensions (Intel® SGX)

Intel SGX custom exception handler

Sangho_L_ — Mon, 14 Mar 2016 23:31:45 GMT

Hello, I tried to use a custom exception handler inside an enclave with real hardware, but it wasn't called. #include "sgx_trts_exception.h" int ex_handler(sgx_exception_info_t *info) { printf("vec: %d, type: %d, eip: %u\n", info->exception_vector, info->exception_type, info->cpu_context.eip); return 1; } ... void init() { ... void *handler = sgx_register_exception_handler(0 /* and 1 */, &ex_handler); printf("handler: %u\n", handler); ... // divide by zero } sgx_register_exception_handler returned a non-zero value, but when the enclave executed a DIV0 instruction, it was just killed without calling the custom exception handler. Are there any other procedures to register a custom exception handler?

Several notes:

Derek_B_Intel — Tue, 15 Mar 2016 15:54:25 GMT

Several notes:
1. OCalls are not allowed in exception handlers. The "printf" function is assumed to be supported as an OCall since I/O instructions are not supported within an enclave.

2. For the exception handler itself, "ex_handler", the return value should be:
#define EXCEPTION_CONTINUE_SEARCH 0
#define EXCEPTION_CONTINUE_EXECUTION -1

Thanks for your answer.

Sangho_L_ — Wed, 16 Mar 2016 18:54:24 GMT

Thanks for your answer. Now I want to advance RIP to ignore the faulting instruction, but I can't find a way to access TCS or SSA to change the stored RIP. Could you let me know how can I access such data structures?

The exception handler has one

Juan_d_Intel — Wed, 30 Mar 2016 18:29:26 GMT

The exception handler has one parameter, a pointer to sgx_exception_info_t.

The sgx_cpu_context_t part of this parameter is loaded with the CPU registers from the SSA frame.

After the exception handler returns and only if it returns EXCEPTION_CONTINUE_EXECUTION, which indicates the exception has been handled, the updated CPU context values will be stored back into the SSA frame.