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    <title>topic Hi, in Intel® Software Guard Extensions (Intel® SGX)</title>
    <link>https://community.intel.com/t5/Intel-Software-Guard-Extensions/Handling-exceptions-inside-enclave/m-p/1111610#M1326</link>
    <description>&lt;P&gt;Hi,&lt;/P&gt;

&lt;P&gt;&lt;SPAN style="font-size: 1em;"&gt;&amp;nbsp; &amp;nbsp;To handle exceptions occurred by SIGSEGV we need signal handlers.Technically, you can catch segfaults with a signal handler for SIGSEGV. The handler is supported only if signal.h header file is available,but the header file is not supported inside enclave. &lt;/SPAN&gt;&lt;/P&gt;

&lt;P&gt;&lt;SPAN style="font-size: 1em;"&gt;For further information please refer to the&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN style="color: rgb(36, 39, 41); font-family: Arial, &amp;quot;Helvetica Neue&amp;quot;, Helvetica, sans-serif; font-size: 15px;"&gt;&amp;nbsp;&lt;/SPAN&gt;Unsupported C Standard Functions (pg. 353)&amp;nbsp;from &lt;A href="https://community.intel.com/legacyfs/online/drupal_files/managed/b4/cf/Intel-SGX-SDK-Developer-Reference-for-Windows-OS.pdf"&gt;here&lt;/A&gt;.&amp;nbsp;&lt;/P&gt;

&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
    <pubDate>Thu, 25 May 2017 12:01:26 GMT</pubDate>
    <dc:creator>Anusha_K_Intel</dc:creator>
    <dc:date>2017-05-25T12:01:26Z</dc:date>
    <item>
      <title>Handling exceptions inside enclave</title>
      <link>https://community.intel.com/t5/Intel-Software-Guard-Extensions/Handling-exceptions-inside-enclave/m-p/1111607#M1323</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;

&lt;P&gt;I'm trying to handle hardware exceptions inside the enclave. From the references given, I came to know that the function "sgx_register_exception_handler()" can be used to handle exceptions inside the enclave. But trying some sample code, it seems it can't handle the memory based exception (SIGSEGV). I'm able to handle the arithmetic errors (SIGFPE).&lt;/P&gt;

&lt;P&gt;Is there any to do handle the same?&lt;/P&gt;

&lt;P&gt;I have registered the handler as: sgx_register_exception_handler(10,exception_handler);&lt;/P&gt;

&lt;P&gt;I saw the post here :&amp;nbsp;https://software.intel.com/en-us/forums/intel-software-guard-extensions-intel-sgx/topic/671518&lt;BR /&gt;
	It mentions that " If an exception happens while running within the enclave, the OS will search for registered exception handlers and will find what sgx_urts.dll has registered. When the sgx_urts.dll's handler gets control, ECALLs into the enclave again to execute the trusted exception handler.". But in my case it is not able to call the registered exception handler.&lt;/P&gt;

&lt;P&gt;Thanks,&lt;/P&gt;

&lt;P&gt;Subhendu.&lt;/P&gt;</description>
      <pubDate>Fri, 19 May 2017 18:17:55 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Software-Guard-Extensions/Handling-exceptions-inside-enclave/m-p/1111607#M1323</guid>
      <dc:creator>Subhendu_M_</dc:creator>
      <dc:date>2017-05-19T18:17:55Z</dc:date>
    </item>
    <item>
      <title>Hi,</title>
      <link>https://community.intel.com/t5/Intel-Software-Guard-Extensions/Handling-exceptions-inside-enclave/m-p/1111608#M1324</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;

&lt;P&gt;The exception handler has one parameter, a pointer to sgx_exception_info_t. The sgx_cpu_context_t part of this parameter is loaded with the CPU registers from the SSA frame. After the exception handler returns and only if it returns EXCEPTION_CONTINUE_EXECUTION, which indicates the exception has been handled, the updated CPU context values will be stored back into the SSA frame.&lt;/P&gt;

&lt;P&gt;If you register an exception handler using sgx_register_exception_handler( ), then your exception handler will be called with a sgx_exception_info_t structure. The info-&amp;gt;exception_type and info-&amp;gt;exception_vector will define the type and vector from EXITINFO.&amp;nbsp;&lt;/P&gt;

&lt;P&gt;Note: your exception handler will not be called if you reenter the enclave after an interrupt or an exception that is not recorded in EXITINFO.&lt;/P&gt;

&lt;P&gt;-Surenthar&lt;/P&gt;</description>
      <pubDate>Tue, 23 May 2017 06:26:36 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Software-Guard-Extensions/Handling-exceptions-inside-enclave/m-p/1111608#M1324</guid>
      <dc:creator>Surenthar_S_Intel</dc:creator>
      <dc:date>2017-05-23T06:26:36Z</dc:date>
    </item>
    <item>
      <title>In the case of SIGSEGV errors</title>
      <link>https://community.intel.com/t5/Intel-Software-Guard-Extensions/Handling-exceptions-inside-enclave/m-p/1111609#M1325</link>
      <description>&lt;P&gt;In the case of SIGSEGV errors, the error handling mechanism is not going in the 2nd phase to call my registered handler.&lt;BR /&gt;
	Is there a specific reason to not handle SIGSEGV errors?&lt;/P&gt;

&lt;P&gt;thanks,&lt;/P&gt;

&lt;P&gt;Subhendu.&lt;BR /&gt;
	&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Thu, 25 May 2017 06:20:22 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Software-Guard-Extensions/Handling-exceptions-inside-enclave/m-p/1111609#M1325</guid>
      <dc:creator>Subhendu_M_</dc:creator>
      <dc:date>2017-05-25T06:20:22Z</dc:date>
    </item>
    <item>
      <title>Hi,</title>
      <link>https://community.intel.com/t5/Intel-Software-Guard-Extensions/Handling-exceptions-inside-enclave/m-p/1111610#M1326</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;

&lt;P&gt;&lt;SPAN style="font-size: 1em;"&gt;&amp;nbsp; &amp;nbsp;To handle exceptions occurred by SIGSEGV we need signal handlers.Technically, you can catch segfaults with a signal handler for SIGSEGV. The handler is supported only if signal.h header file is available,but the header file is not supported inside enclave. &lt;/SPAN&gt;&lt;/P&gt;

&lt;P&gt;&lt;SPAN style="font-size: 1em;"&gt;For further information please refer to the&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN style="color: rgb(36, 39, 41); font-family: Arial, &amp;quot;Helvetica Neue&amp;quot;, Helvetica, sans-serif; font-size: 15px;"&gt;&amp;nbsp;&lt;/SPAN&gt;Unsupported C Standard Functions (pg. 353)&amp;nbsp;from &lt;A href="https://community.intel.com/legacyfs/online/drupal_files/managed/b4/cf/Intel-SGX-SDK-Developer-Reference-for-Windows-OS.pdf"&gt;here&lt;/A&gt;.&amp;nbsp;&lt;/P&gt;

&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Thu, 25 May 2017 12:01:26 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Software-Guard-Extensions/Handling-exceptions-inside-enclave/m-p/1111610#M1326</guid>
      <dc:creator>Anusha_K_Intel</dc:creator>
      <dc:date>2017-05-25T12:01:26Z</dc:date>
    </item>
    <item>
      <title>But I'm able to get the</title>
      <link>https://community.intel.com/t5/Intel-Software-Guard-Extensions/Handling-exceptions-inside-enclave/m-p/1111611#M1327</link>
      <description>&lt;P&gt;But I'm able to get the control when there is an SIGFPE error to the registered handler. That also requires to have the signal.h header included inside the enclave.&lt;/P&gt;

&lt;P&gt;Thanks,&lt;/P&gt;

&lt;P&gt;Subhendu&lt;/P&gt;</description>
      <pubDate>Thu, 25 May 2017 12:27:26 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Software-Guard-Extensions/Handling-exceptions-inside-enclave/m-p/1111611#M1327</guid>
      <dc:creator>Subhendu_M_</dc:creator>
      <dc:date>2017-05-25T12:27:26Z</dc:date>
    </item>
    <item>
      <title>Hi,</title>
      <link>https://community.intel.com/t5/Intel-Software-Guard-Extensions/Handling-exceptions-inside-enclave/m-p/1111612#M1328</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;

&lt;P&gt;According to the document, it is given that these functions are not supported inside enclave, So you need to write your own function to handle this exception by using an OCALL. Can you share your code so we can look into the error which your facing?&lt;/P&gt;

&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Thu, 25 May 2017 12:43:21 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Software-Guard-Extensions/Handling-exceptions-inside-enclave/m-p/1111612#M1328</guid>
      <dc:creator>Anusha_K_Intel</dc:creator>
      <dc:date>2017-05-25T12:43:21Z</dc:date>
    </item>
    <item>
      <title>The code is in the repo:</title>
      <link>https://community.intel.com/t5/Intel-Software-Guard-Extensions/Handling-exceptions-inside-enclave/m-p/1111613#M1329</link>
      <description>&lt;P&gt;The code is in the repo:&lt;/P&gt;

&lt;P&gt;&lt;A href="https://github.com/deathholes/sgx-enclave-sample"&gt;https://github.com/deathholes/sgx-enclave-sample&lt;/A&gt;&lt;/P&gt;

&lt;P&gt;The file Enclave/Enclave.cpp contains the ecall functions:&lt;/P&gt;

&lt;P&gt;There are two errors in the function, namely an arithmetic error(SIGFPE) at line 80 and an address boundary error(SIGSEGV) at line 84.&lt;/P&gt;

&lt;P&gt;Output for the arithmetic error is:&lt;/P&gt;

&lt;BLOCKQUOTE&gt;
	&lt;P&gt;&lt;BR /&gt;
		before: RANDOM STRING&lt;BR /&gt;
		String : registered&lt;BR /&gt;
		String : registered[sig_handler sig_handler.cpp:94] signal handler is triggered&lt;BR /&gt;
		[sig_handler sig_handler.cpp:112] exception on ERESUME&lt;BR /&gt;
		[sig_handler sig_handler.cpp:94] signal handler is triggered&lt;BR /&gt;
		[sig_handler sig_handler.cpp:112] exception on ERESUME&lt;BR /&gt;
		[sig_handler sig_handler.cpp:150] NOT enclave signal&lt;BR /&gt;
		fish: “./app” terminated by signal SIGFPE (Floating point exception)&lt;/P&gt;
&lt;/BLOCKQUOTE&gt;

&lt;P&gt;&lt;BR /&gt;
	Clearly, the signal handler is triggered here. Also, putting a breakpoint at the entry of the handler( line # 11), in the debug mode, the control is reaching there.&lt;/P&gt;

&lt;P&gt;For the address boundary error, the Output is:&lt;/P&gt;

&lt;BLOCKQUOTE&gt;
	&lt;P&gt;&lt;BR /&gt;
		before: RANDOM STRING&lt;BR /&gt;
		String : registered&lt;BR /&gt;
		String : registered[sig_handler sig_handler.cpp:94] signal handler is triggered&lt;BR /&gt;
		[sig_handler sig_handler.cpp:112] exception on ERESUME&lt;BR /&gt;
		[sig_handler sig_handler.cpp:150] NOT enclave signal&lt;BR /&gt;
		fish: “./app” terminated by signal SIGSEGV (Address boundary error)&lt;/P&gt;
&lt;/BLOCKQUOTE&gt;

&lt;P&gt;&lt;BR /&gt;
	Here there is no call to the signal handler. Putting the same breakpoint doesn't help.&lt;BR /&gt;
	I tried this for SIGILL error also.&lt;/P&gt;

&lt;P&gt;The code is:&lt;/P&gt;

&lt;BLOCKQUOTE&gt;
	&lt;P&gt;vector&amp;lt;int&amp;gt; v;&lt;BR /&gt;
		v.resize(1);&lt;BR /&gt;
		v.at(150) = 5;&lt;/P&gt;
&lt;/BLOCKQUOTE&gt;

&lt;P&gt;It also behaves the same as SIGSEGV error.&lt;/P&gt;

&lt;P&gt;Thanks,&lt;/P&gt;

&lt;P&gt;Subhendu.&lt;/P&gt;</description>
      <pubDate>Thu, 25 May 2017 13:25:17 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Software-Guard-Extensions/Handling-exceptions-inside-enclave/m-p/1111613#M1329</guid>
      <dc:creator>Subhendu_M_</dc:creator>
      <dc:date>2017-05-25T13:25:17Z</dc:date>
    </item>
    <item>
      <title>Hello, </title>
      <link>https://community.intel.com/t5/Intel-Software-Guard-Extensions/Handling-exceptions-inside-enclave/m-p/1111614#M1330</link>
      <description>&lt;P&gt;Hello,&amp;nbsp;&lt;/P&gt;

&lt;P&gt;I am interested in handling SIGSEGV inside the enclave too. Did you get any further with this? If you can't do it by registering a custom handler through `&lt;SPAN style="font-size: 1em;"&gt;sgx_register_exception_handler` is there an alternative way of doing it? I am especially keen to know how I can modify the context stored in the SSA and get past the offending instruction.&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;

&lt;P&gt;&amp;nbsp;&lt;/P&gt;

&lt;P&gt;&lt;SPAN style="font-size: 1em;"&gt;Thanks,&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Mon, 11 Sep 2017 11:09:56 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Software-Guard-Extensions/Handling-exceptions-inside-enclave/m-p/1111614#M1330</guid>
      <dc:creator>Divya_M_</dc:creator>
      <dc:date>2017-09-11T11:09:56Z</dc:date>
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