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    <title>topic Intel SGX doesn't trust the in Intel® Software Guard Extensions (Intel® SGX)</title>
    <link>https://community.intel.com/t5/Intel-Software-Guard-Extensions/EPC-protection/m-p/1134301#M2004</link>
    <description>&lt;P&gt;Intel SGX doesn't trust the OS, so it maintains the EPCM to support page permission check for EPC pages. The security check is performed by extending the page miss handler (PMH).&lt;/P&gt;

&lt;P&gt;Please refer to &lt;A href="https://eprint.iacr.org/2016/086.pdf" target="_blank"&gt;https://eprint.iacr.org/2016/086.pdf&lt;/A&gt;, page 93, Sec. 6.2 for more details.&lt;/P&gt;</description>
    <pubDate>Sat, 24 Jun 2017 13:14:46 GMT</pubDate>
    <dc:creator>yunfeng7854</dc:creator>
    <dc:date>2017-06-24T13:14:46Z</dc:date>
    <item>
      <title>EPC protection</title>
      <link>https://community.intel.com/t5/Intel-Software-Guard-Extensions/EPC-protection/m-p/1134300#M2003</link>
      <description>&lt;P&gt;Hi folks,&lt;/P&gt;

&lt;P&gt;Do you know how SGX makes EPC invisible to OS? I know that there is an ownership mechanism using labels for different enclaves to make sure every enclave is accessing just to its own page inside the EPC; is there a similar mechanism for OS as well? it seems&amp;nbsp;SGX needs more to prevent the adversary OS from EPC?&amp;nbsp;&lt;/P&gt;

&lt;P&gt;&amp;nbsp;&lt;/P&gt;

&lt;P&gt;thanks&lt;/P&gt;

&lt;P&gt;Meysam&lt;/P&gt;</description>
      <pubDate>Fri, 23 Jun 2017 23:07:40 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Software-Guard-Extensions/EPC-protection/m-p/1134300#M2003</guid>
      <dc:creator>Meysam_t_</dc:creator>
      <dc:date>2017-06-23T23:07:40Z</dc:date>
    </item>
    <item>
      <title>Intel SGX doesn't trust the</title>
      <link>https://community.intel.com/t5/Intel-Software-Guard-Extensions/EPC-protection/m-p/1134301#M2004</link>
      <description>&lt;P&gt;Intel SGX doesn't trust the OS, so it maintains the EPCM to support page permission check for EPC pages. The security check is performed by extending the page miss handler (PMH).&lt;/P&gt;

&lt;P&gt;Please refer to &lt;A href="https://eprint.iacr.org/2016/086.pdf" target="_blank"&gt;https://eprint.iacr.org/2016/086.pdf&lt;/A&gt;, page 93, Sec. 6.2 for more details.&lt;/P&gt;</description>
      <pubDate>Sat, 24 Jun 2017 13:14:46 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Software-Guard-Extensions/EPC-protection/m-p/1134301#M2004</guid>
      <dc:creator>yunfeng7854</dc:creator>
      <dc:date>2017-06-24T13:14:46Z</dc:date>
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