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    <title>topic SSA and TCS Data Structure in SGX in Intel Confidential Computing</title>
    <link>https://community.intel.com/t5/Intel-Confidential-Computing/SSA-and-TCS-Data-Structure-in-SGX/m-p/1069100#M251</link>
    <description>&lt;P&gt;Hi,&lt;/P&gt;

&lt;P&gt;&lt;SPAN style="font-size: 12px; line-height: 18px;"&gt;I want to advance RIP to ignore the faulting instruction, but I can't find a way to access TCS or SSA to change the stored RIP.&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN style="font-size: 12px; line-height: 18px;"&gt;Could you let me know how can I access such data structures available in SGX?&lt;/SPAN&gt;&lt;/P&gt;

&lt;P&gt;&lt;SPAN style="font-size: 12px; line-height: 18px;"&gt;-Thanks&lt;/SPAN&gt;&lt;/P&gt;</description>
    <pubDate>Thu, 08 Sep 2016 06:04:33 GMT</pubDate>
    <dc:creator>SAM_R_2</dc:creator>
    <dc:date>2016-09-08T06:04:33Z</dc:date>
    <item>
      <title>SSA and TCS Data Structure in SGX</title>
      <link>https://community.intel.com/t5/Intel-Confidential-Computing/SSA-and-TCS-Data-Structure-in-SGX/m-p/1069100#M251</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;

&lt;P&gt;&lt;SPAN style="font-size: 12px; line-height: 18px;"&gt;I want to advance RIP to ignore the faulting instruction, but I can't find a way to access TCS or SSA to change the stored RIP.&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN style="font-size: 12px; line-height: 18px;"&gt;Could you let me know how can I access such data structures available in SGX?&lt;/SPAN&gt;&lt;/P&gt;

&lt;P&gt;&lt;SPAN style="font-size: 12px; line-height: 18px;"&gt;-Thanks&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Thu, 08 Sep 2016 06:04:33 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Confidential-Computing/SSA-and-TCS-Data-Structure-in-SGX/m-p/1069100#M251</guid>
      <dc:creator>SAM_R_2</dc:creator>
      <dc:date>2016-09-08T06:04:33Z</dc:date>
    </item>
    <item>
      <title>Hi Sam,</title>
      <link>https://community.intel.com/t5/Intel-Confidential-Computing/SSA-and-TCS-Data-Structure-in-SGX/m-p/1069101#M252</link>
      <description>&lt;P&gt;Hi Sam,&lt;/P&gt;

&lt;P&gt;The exception handler has one parameter, a pointer to&amp;nbsp;&lt;SPAN style="font-size: 1em; line-height: 1.5;"&gt;sgx_exception_info_t.&lt;/SPAN&gt;&lt;/P&gt;

&lt;P&gt;The sgx_cpu_context_t part of this parameter is loaded with the&amp;nbsp;&lt;SPAN style="font-size: 1em; line-height: 1.5;"&gt;CPU registers from the SSA frame.&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;

&lt;P&gt;&lt;SPAN style="font-size: 1em; line-height: 1.5;"&gt;After the exception handler returns and only if it returns&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN style="font-size: 1em; line-height: 1.5;"&gt;EXCEPTION_CONTINUE_EXECUTION, which indicates the exception has&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN style="font-size: 1em; line-height: 1.5;"&gt;been handled, the updated CPU context values will be stored back&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN style="font-size: 1em; line-height: 1.5;"&gt;into the SSA frame.&lt;/SPAN&gt;&lt;/P&gt;

&lt;P&gt;Thanks and Regards,&lt;BR /&gt;
	Surenthar Selvaraj&lt;/P&gt;</description>
      <pubDate>Thu, 08 Sep 2016 06:41:35 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Confidential-Computing/SSA-and-TCS-Data-Structure-in-SGX/m-p/1069101#M252</guid>
      <dc:creator>Surenthar_S_Intel</dc:creator>
      <dc:date>2016-09-08T06:41:35Z</dc:date>
    </item>
    <item>
      <title>Thanks Surenthar</title>
      <link>https://community.intel.com/t5/Intel-Confidential-Computing/SSA-and-TCS-Data-Structure-in-SGX/m-p/1069102#M253</link>
      <description>&lt;P&gt;Thanks Surenthar&lt;/P&gt;</description>
      <pubDate>Thu, 08 Sep 2016 06:49:43 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Confidential-Computing/SSA-and-TCS-Data-Structure-in-SGX/m-p/1069102#M253</guid>
      <dc:creator>SAM_R_2</dc:creator>
      <dc:date>2016-09-08T06:49:43Z</dc:date>
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