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    <title>topic Thanks for your info.... in Intel® Software Guard Extensions (Intel® SGX)</title>
    <link>https://community.intel.com/t5/Intel-Software-Guard-Extensions/Signature-Padding-in-SGX/m-p/1069220#M256</link>
    <description>&lt;P&gt;Thanks for your info....&lt;/P&gt;</description>
    <pubDate>Thu, 08 Sep 2016 06:49:55 GMT</pubDate>
    <dc:creator>SAM_R_2</dc:creator>
    <dc:date>2016-09-08T06:49:55Z</dc:date>
    <item>
      <title>Signature Padding in SGX</title>
      <link>https://community.intel.com/t5/Intel-Software-Guard-Extensions/Signature-Padding-in-SGX/m-p/1069218#M254</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;

&lt;P style="word-wrap: break-word; font-size: 12px;"&gt;From this white paper :&amp;nbsp;&lt;A href="https://software.intel.com/en-us/articles/innovative-technology-for-cpu-based-attestation-and-sealing" style="line-height: 1.5; cursor: pointer;"&gt;https://software.intel.com/en-us/articles/innovative-technology-for-cpu-based-attestation-and-sealing&lt;/A&gt;&lt;/P&gt;

&lt;P style="word-wrap: break-word; font-size: 12px;"&gt;If you look at Table 2-2 in the reference, it mentions that the padding in the SECS is derived from the signature (presumably from the SIGSTRUCT).&lt;/P&gt;

&lt;P style="word-wrap: break-word; font-size: 12px;"&gt;- Thanks&lt;/P&gt;</description>
      <pubDate>Thu, 08 Sep 2016 06:07:14 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Software-Guard-Extensions/Signature-Padding-in-SGX/m-p/1069218#M254</guid>
      <dc:creator>SAM_R_2</dc:creator>
      <dc:date>2016-09-08T06:07:14Z</dc:date>
    </item>
    <item>
      <title>Hi Sam,</title>
      <link>https://community.intel.com/t5/Intel-Software-Guard-Extensions/Signature-Padding-in-SGX/m-p/1069219#M255</link>
      <description>&lt;P&gt;Hi Sam,&lt;/P&gt;

&lt;P&gt;Signature Padding is included as an additional defense against&amp;nbsp;&lt;SPAN style="font-size: 1em; line-height: 1.5;"&gt;padding attacks on the SIGSTRUCT signature. The signature&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN style="font-size: 1em; line-height: 1.5;"&gt;padding being included in SGX keys results in the key being &lt;/SPAN&gt;&lt;SPAN style="font-size: 1em; line-height: 1.5;"&gt;bound to a correctly composed signature over the enclave’s&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN style="font-size: 1em; line-height: 1.5;"&gt;SIGSTRUCT and not key that signed the contents of SIGSTRUCT&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN style="font-size: 1em; line-height: 1.5;"&gt;[MRSIGNER] or ISVSVN.&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;

&lt;P&gt;Thanks and Regards,&lt;BR /&gt;
	Surenthar Selvaraj&lt;/P&gt;</description>
      <pubDate>Thu, 08 Sep 2016 06:41:05 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Software-Guard-Extensions/Signature-Padding-in-SGX/m-p/1069219#M255</guid>
      <dc:creator>Surenthar_S_Intel</dc:creator>
      <dc:date>2016-09-08T06:41:05Z</dc:date>
    </item>
    <item>
      <title>Thanks for your info....</title>
      <link>https://community.intel.com/t5/Intel-Software-Guard-Extensions/Signature-Padding-in-SGX/m-p/1069220#M256</link>
      <description>&lt;P&gt;Thanks for your info....&lt;/P&gt;</description>
      <pubDate>Thu, 08 Sep 2016 06:49:55 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Software-Guard-Extensions/Signature-Padding-in-SGX/m-p/1069220#M256</guid>
      <dc:creator>SAM_R_2</dc:creator>
      <dc:date>2016-09-08T06:49:55Z</dc:date>
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