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    <title>topic Re: Re:Number of Available Memory Encryption Engine for Multi Cores Single Server in Intel® Software Guard Extensions (Intel® SGX)</title>
    <link>https://community.intel.com/t5/Intel-Software-Guard-Extensions/Number-of-Available-Memory-Encryption-Engine-for-Multi-Cores/m-p/1518548#M5896</link>
    <description>&lt;P&gt;I just find that here is Intel SGX community... I am sorry. Wan, thanks for your previous answer!&lt;/P&gt;</description>
    <pubDate>Tue, 29 Aug 2023 01:45:10 GMT</pubDate>
    <dc:creator>Sean_</dc:creator>
    <dc:date>2023-08-29T01:45:10Z</dc:date>
    <item>
      <title>Number of Available Memory Encryption Engine for Multi Cores Single Server</title>
      <link>https://community.intel.com/t5/Intel-Software-Guard-Extensions/Number-of-Available-Memory-Encryption-Engine-for-Multi-Cores/m-p/1515696#M5873</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;I wonder for single server with multi cpus and logical cores, if there are ONLY ONE memory encryption engine hardware on the server?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;In that case, if I run multiple enclaves on the same server, the programs of the many enclaves need to wait for the recourse of the ONLY memory encryption engine hardware to do address translation, decryption, etc?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;For a multi-cpu and multi-core server, does it have SGX hardware on each chip, or all cpus share a only one SGX hardware?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thank you very much.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Best,&lt;/P&gt;&lt;P&gt;-Sean.&lt;/P&gt;</description>
      <pubDate>Sat, 19 Aug 2023 09:59:35 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Software-Guard-Extensions/Number-of-Available-Memory-Encryption-Engine-for-Multi-Cores/m-p/1515696#M5873</guid>
      <dc:creator>Sean_</dc:creator>
      <dc:date>2023-08-19T09:59:35Z</dc:date>
    </item>
    <item>
      <title>Re:Number of Available Memory Encryption Engine for Multi Cores Single Server</title>
      <link>https://community.intel.com/t5/Intel-Software-Guard-Extensions/Number-of-Available-Memory-Encryption-Engine-for-Multi-Cores/m-p/1516333#M5883</link>
      <description>&lt;P&gt;&lt;SPAN style="font-size: 16px;"&gt;Hello Sean_,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 16px;"&gt;Thanks for reaching out to us.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 16px;"&gt;Let me check with relevant team and I'll update here at the earliest.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 16px;"&gt;Regards,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 16px;"&gt;Wam&lt;/SPAN&gt;&lt;/P&gt;&lt;BR /&gt;</description>
      <pubDate>Tue, 22 Aug 2023 04:46:23 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Software-Guard-Extensions/Number-of-Available-Memory-Encryption-Engine-for-Multi-Cores/m-p/1516333#M5883</guid>
      <dc:creator>Wan_Intel</dc:creator>
      <dc:date>2023-08-22T04:46:23Z</dc:date>
    </item>
    <item>
      <title>Re:Number of Available Memory Encryption Engine for Multi Cores Single Server</title>
      <link>https://community.intel.com/t5/Intel-Software-Guard-Extensions/Number-of-Available-Memory-Encryption-Engine-for-Multi-Cores/m-p/1517052#M5884</link>
      <description>&lt;P&gt;&lt;SPAN style="font-size: 16px;"&gt;Hello Sean_,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 16px;"&gt;Thanks for your patience.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 16px;"&gt;We've received feedback from relevant team.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 16px;"&gt;For a multi-cpu, multi-core server, each CPU has its own set of hardware resources. i.e. each CPU would have its own SGX hardware including the memory encryption engine (MEE).&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 16px;"&gt;SGX is designed to provide enclave-based security for each core so that enclaves are secure even in a multi-CPU multi-core environment. So the resources are not shared among the CPUs.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 16px;"&gt;Regards,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 16px;"&gt;Wan&lt;/SPAN&gt;&lt;/P&gt;&lt;BR /&gt;</description>
      <pubDate>Wed, 23 Aug 2023 23:54:34 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Software-Guard-Extensions/Number-of-Available-Memory-Encryption-Engine-for-Multi-Cores/m-p/1517052#M5884</guid>
      <dc:creator>Wan_Intel</dc:creator>
      <dc:date>2023-08-23T23:54:34Z</dc:date>
    </item>
    <item>
      <title>Re: Re:Number of Available Memory Encryption Engine for Multi Cores Single Server</title>
      <link>https://community.intel.com/t5/Intel-Software-Guard-Extensions/Number-of-Available-Memory-Encryption-Engine-for-Multi-Cores/m-p/1518546#M5895</link>
      <description>&lt;P&gt;Hello Wan,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thanks for your reply!&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;One last thing to comfirm --- does your answer also applies for Azure Virtual Machine (e.g., DC8ds_v3)? I.e., Each vCPU of DC8ds_v3 has its own set of SGX Intel Hardware?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Best,&lt;/P&gt;&lt;P&gt;-Xian&lt;/P&gt;</description>
      <pubDate>Tue, 29 Aug 2023 01:36:46 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Software-Guard-Extensions/Number-of-Available-Memory-Encryption-Engine-for-Multi-Cores/m-p/1518546#M5895</guid>
      <dc:creator>Sean_</dc:creator>
      <dc:date>2023-08-29T01:36:46Z</dc:date>
    </item>
    <item>
      <title>Re: Re:Number of Available Memory Encryption Engine for Multi Cores Single Server</title>
      <link>https://community.intel.com/t5/Intel-Software-Guard-Extensions/Number-of-Available-Memory-Encryption-Engine-for-Multi-Cores/m-p/1518548#M5896</link>
      <description>&lt;P&gt;I just find that here is Intel SGX community... I am sorry. Wan, thanks for your previous answer!&lt;/P&gt;</description>
      <pubDate>Tue, 29 Aug 2023 01:45:10 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Software-Guard-Extensions/Number-of-Available-Memory-Encryption-Engine-for-Multi-Cores/m-p/1518548#M5896</guid>
      <dc:creator>Sean_</dc:creator>
      <dc:date>2023-08-29T01:45:10Z</dc:date>
    </item>
    <item>
      <title>Re:Number of Available Memory Encryption Engine for Multi Cores Single Server</title>
      <link>https://community.intel.com/t5/Intel-Software-Guard-Extensions/Number-of-Available-Memory-Encryption-Engine-for-Multi-Cores/m-p/1519228#M5897</link>
      <description>&lt;P&gt;&lt;SPAN style="font-size: 16px;"&gt;Hello Sean_,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 16px;"&gt;Thanks for your question.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 16px;"&gt;If you need additional information from Intel, please submit a new question as this thread will no longer be monitored.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 16px;"&gt;Regards,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 16px;"&gt;Wan&lt;/SPAN&gt;&lt;/P&gt;&lt;BR /&gt;</description>
      <pubDate>Thu, 31 Aug 2023 02:34:44 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Software-Guard-Extensions/Number-of-Available-Memory-Encryption-Engine-for-Multi-Cores/m-p/1519228#M5897</guid>
      <dc:creator>Wan_Intel</dc:creator>
      <dc:date>2023-08-31T02:34:44Z</dc:date>
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