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    <title>topic No, no page fault will the in Intel® Software Guard Extensions (Intel® SGX)</title>
    <link>https://community.intel.com/t5/Intel-Software-Guard-Extensions/Reading-EXITINFO/m-p/1083418#M618</link>
    <description>&lt;P&gt;No, no page fault will the reported. Your laptop will only report exceptions described in the VECTOR Field Definition.&lt;/P&gt;

&lt;P&gt;In addition to the flow explained above, the sgx_urts.dll installs an exception handler before ECALLing into the enclave. If an exception happens while running within the enclave, the OS will search for registered exception handlers and will find what sgx_urts.dll has registered. When the sgx_urts.dll's handler gets control, ECALLs into the enclave again to execute the trusted exception handler. The enclave's handler access the information stored in the SSA and gives control to any exception handler the enclave might have registered. If the enclave handles the exception (EXCEPTION_CONTINUE_EXECUTION), sgx_urts.dll returns the same code to the OS, which then ERESUMEs and execution continues inside the enclave at the point where the exception (AEX) occurred. If the enclave doesn't handle the exception (EXCEPTION_EXECUTE_HANDLER) the OS will continue searching up the stack for a&amp;nbsp;handler and eventually will abort the application if no other is found.&lt;/P&gt;</description>
    <pubDate>Thu, 09 Jun 2016 13:41:23 GMT</pubDate>
    <dc:creator>Juan_d_Intel</dc:creator>
    <dc:date>2016-06-09T13:41:23Z</dc:date>
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      <title>Reading EXITINFO?</title>
      <link>https://community.intel.com/t5/Intel-Software-Guard-Extensions/Reading-EXITINFO/m-p/1083412#M612</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;

&lt;P&gt;I'm trying to read EXITINFO from SSA to detect whether the current thread has been interrupted in the past. But I don't have enough information to locate the current SSA in the memory. Can you guys shed some light on where to start?&lt;/P&gt;

&lt;P&gt;Fan&lt;/P&gt;

&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Thu, 02 Jun 2016 18:03:23 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Software-Guard-Extensions/Reading-EXITINFO/m-p/1083412#M612</guid>
      <dc:creator>Fan</dc:creator>
      <dc:date>2016-06-02T18:03:23Z</dc:date>
    </item>
    <item>
      <title>If you register an exception</title>
      <link>https://community.intel.com/t5/Intel-Software-Guard-Extensions/Reading-EXITINFO/m-p/1083413#M613</link>
      <description>&lt;P&gt;If you register an exception handler using sgx_register_exception_handler( ), then&amp;nbsp;your exception handler will be called with a sgx_exception_info_t structure.&amp;nbsp;&lt;/P&gt;

&lt;P&gt;The info-&amp;gt;exception_type and info-&amp;gt;exception_vector will define the type and vector from EXITINFO.&lt;/P&gt;

&lt;P&gt;Note: your exception handler will not be called if you reenter the enclave after an interrupt or an exception that is not recorded in EXITINFO.&lt;/P&gt;</description>
      <pubDate>Thu, 02 Jun 2016 19:10:39 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Software-Guard-Extensions/Reading-EXITINFO/m-p/1083413#M613</guid>
      <dc:creator>Mark_S_Intel2</dc:creator>
      <dc:date>2016-06-02T19:10:39Z</dc:date>
    </item>
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      <title>That's exactly what I've been</title>
      <link>https://community.intel.com/t5/Intel-Software-Guard-Extensions/Reading-EXITINFO/m-p/1083414#M614</link>
      <description>&lt;P&gt;That's exactly what I've been looking for.&lt;/P&gt;

&lt;P&gt;Just one thing: If I understand correctly, this handler will be called by ERESUME, when reenter the enclave after an interrupt or an exception. But ERESUME is called by untrusted application. Can the untrusted application bypass the exception handlers somehow?&lt;/P&gt;

&lt;P&gt;Fan&lt;/P&gt;

&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Thu, 02 Jun 2016 19:47:08 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Software-Guard-Extensions/Reading-EXITINFO/m-p/1083414#M614</guid>
      <dc:creator>Fan</dc:creator>
      <dc:date>2016-06-02T19:47:08Z</dc:date>
    </item>
    <item>
      <title>Quote:Mark S. (Intel) wrote:</title>
      <link>https://community.intel.com/t5/Intel-Software-Guard-Extensions/Reading-EXITINFO/m-p/1083415#M615</link>
      <description>&lt;P&gt;&lt;/P&gt;&lt;BLOCKQUOTE&gt;Mark S. (Intel) wrote:&lt;BR /&gt;&lt;P&gt;&lt;/P&gt;

&lt;P&gt;If you register an exception handler using sgx_register_exception_handler( ), then&amp;nbsp;your exception handler will be called with a sgx_exception_info_t structure.&amp;nbsp;&lt;/P&gt;

&lt;P&gt;The info-&amp;gt;exception_type and info-&amp;gt;exception_vector will define the type and vector from EXITINFO.&lt;/P&gt;

&lt;P&gt;Note: your exception handler will not be called if you reenter the enclave after an interrupt or an exception that is not recorded in EXITINFO.&lt;/P&gt;

&lt;P&gt;&lt;/P&gt;&lt;/BLOCKQUOTE&gt;&lt;P&gt;&lt;/P&gt;

&lt;P style="font-size: 13.008px; line-height: 19.512px;"&gt;First, a quick question: will page fault be reported?&amp;nbsp;&lt;/P&gt;

&lt;P style="font-size: 13.008px; line-height: 19.512px;"&gt;Second, come to think of it I'm wondering how is this "enclave exception handler" mechanism realized.&amp;nbsp;If I understand correctly, when an AEX happens, firstly a system exception handler will be called.&amp;nbsp;Afterward,&amp;nbsp;the AEP will be called (by pointing RIP to AEP), which will eventually call&amp;nbsp;ERESUME&amp;nbsp;to reenter the enclave. But, my question is which TCS is passed to&amp;nbsp;ERESUME.&lt;/P&gt;

&lt;P style="font-size: 13.008px; line-height: 19.512px;"&gt;If the interrupted TCS is passed, then execution will continue from wherever it's left without going to the enclave exception handler. So a different TCS (with OEntry pointed to the enclave exception handlers) must be used. But it is the untrusted application that controls how&amp;nbsp;ERESUME&amp;nbsp;is called. So it seems like enclave exception handlers can be completely bypassed by the untrusted application, no?&lt;/P&gt;</description>
      <pubDate>Thu, 02 Jun 2016 22:05:08 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Software-Guard-Extensions/Reading-EXITINFO/m-p/1083415#M615</guid>
      <dc:creator>Fan</dc:creator>
      <dc:date>2016-06-02T22:05:08Z</dc:date>
    </item>
    <item>
      <title>Hi FAN,</title>
      <link>https://community.intel.com/t5/Intel-Software-Guard-Extensions/Reading-EXITINFO/m-p/1083416#M616</link>
      <description>&lt;P&gt;Hi FAN,&lt;BR /&gt;
	Page fault is reported in SGX.&lt;BR /&gt;
	&lt;STRONG&gt;Enclave Exception Handler Mechanism:&lt;/STRONG&gt;&lt;BR /&gt;
	&lt;STRONG&gt;Handling Exception:&lt;/STRONG&gt;&lt;BR /&gt;
	Asynchronous Exit (AEX) is used to handle the exception in SGX&lt;BR /&gt;
	Faults, exceptions and interrupts initiate the Asynchronous Exit flow.&lt;BR /&gt;
	During AEX, enclave register state is stored in the enclave’s active SSA frame and initialized to a known value prior to leaving the enclave.&lt;BR /&gt;
	The RIP is initialized to an area referred to as the trampoline code&lt;/P&gt;

&lt;P&gt;&lt;STRONG&gt;Resuming From Exceptions:&lt;/STRONG&gt;&lt;BR /&gt;
	On an AEX the RIP is modified to point to the Trampoline area in the untrusted section of the app. This RIP is pushed onto the stack when jumping to the OS handler.&lt;BR /&gt;
	IRET will return the flow control to the app at the Trampoline Area.&lt;BR /&gt;
	The Trampoline will execute the ERESUME instruction. Register state will be restored from the SSA and Execution will&amp;nbsp;resume from the interrupted location.&lt;/P&gt;

&lt;P&gt;TCS can define multiple SSA frames on the SSA stack. AEX pushes content onto the SSA frame and increments the SSA frame&lt;BR /&gt;
	pointer. Last SSA frame state store in TCS will execute, once the ERESUME called.&lt;/P&gt;

&lt;P&gt;Please find the attachment for your reference for more info on Handling Exceptionflow in SGX&lt;/P&gt;</description>
      <pubDate>Fri, 03 Jun 2016 06:23:06 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Software-Guard-Extensions/Reading-EXITINFO/m-p/1083416#M616</guid>
      <dc:creator>Surenthar_S_Intel</dc:creator>
      <dc:date>2016-06-03T06:23:06Z</dc:date>
    </item>
    <item>
      <title>Quote:Surenthar Selvaraj.</title>
      <link>https://community.intel.com/t5/Intel-Software-Guard-Extensions/Reading-EXITINFO/m-p/1083417#M617</link>
      <description>&lt;P&gt;&lt;/P&gt;&lt;BLOCKQUOTE&gt;Surenthar Selvaraj. (Intel) wrote:&lt;BR /&gt;&lt;P&gt;&lt;/P&gt;

&lt;P&gt;Hi FAN,&lt;BR /&gt;
	Page fault is reported in SGX.&lt;BR /&gt;
	&lt;STRONG&gt;Enclave Exception Handler Mechanism:&lt;/STRONG&gt;&lt;BR /&gt;
	&lt;STRONG&gt;Handling Exception:&lt;/STRONG&gt;&lt;BR /&gt;
	Asynchronous Exit (AEX) is used to handle the exception in SGX&lt;BR /&gt;
	Faults, exceptions and interrupts initiate the Asynchronous Exit flow.&lt;BR /&gt;
	During AEX, enclave register state is stored in the enclave’s active SSA frame and initialized to a known value prior to leaving the enclave.&lt;BR /&gt;
	The RIP is initialized to an area referred to as the trampoline code&lt;/P&gt;

&lt;P&gt;&lt;STRONG&gt;Resuming From Exceptions:&lt;/STRONG&gt;&lt;BR /&gt;
	On an AEX the RIP is modified to point to the Trampoline area in the untrusted section of the app. This RIP is pushed onto the stack when jumping to the OS handler.&lt;BR /&gt;
	IRET will return the flow control to the app at the Trampoline Area.&lt;BR /&gt;
	The Trampoline will execute the ERESUME instruction. Register state will be restored from the SSA and Execution will&amp;nbsp;resume from the interrupted location.&lt;/P&gt;

&lt;P&gt;TCS can define multiple SSA frames on the SSA stack. AEX pushes content onto the SSA frame and increments the SSA frame&lt;BR /&gt;
	pointer. Last SSA frame state store in TCS will execute, once the ERESUME called.&lt;/P&gt;

&lt;P&gt;Please find the attachment for your reference for more info on Handling Exceptionflow in SGX&lt;/P&gt;

&lt;P&gt;&lt;SPAN style="font-size: 1em; -webkit-text-size-adjust: 100%;"&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;/BLOCKQUOTE&gt;&lt;P&gt;&lt;/P&gt;

&lt;P&gt;&lt;SPAN style="font-size: 1em; -webkit-text-size-adjust: 100%;"&gt;Thanks! Two comments:&lt;/SPAN&gt;&lt;/P&gt;

&lt;P&gt;&lt;SPAN style="font-size: 1em; -webkit-text-size-adjust: 100%;"&gt;1)&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN style="font-size: 1em; -webkit-text-size-adjust: 100%;"&gt;On my laptop, MISC region is not supported, which means &lt;/SPAN&gt;&lt;SPAN style="font-size: 1em; -webkit-text-size-adjust: 100%;"&gt;SECS.MISCSELECT.EXINFO&lt;/SPAN&gt;&lt;SPAN style="font-size: 1em; -webkit-text-size-adjust: 100%;"&gt;=0.&lt;/SPAN&gt;&lt;SPAN style="font-size: 1em; -webkit-text-size-adjust: 100%;"&gt;&amp;nbsp;Will page fault still be reported?&lt;/SPAN&gt;&lt;/P&gt;

&lt;P&gt;&lt;SPAN style="font-size: 1em; -webkit-text-size-adjust: 100%;"&gt;2) all you said about exception flow makes sense, but you didn't mention when and how the handlers registered by enclaves are called. Can you say more on that?&lt;/SPAN&gt;&lt;/P&gt;

&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Fri, 03 Jun 2016 13:12:51 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Software-Guard-Extensions/Reading-EXITINFO/m-p/1083417#M617</guid>
      <dc:creator>Fan</dc:creator>
      <dc:date>2016-06-03T13:12:51Z</dc:date>
    </item>
    <item>
      <title>No, no page fault will the</title>
      <link>https://community.intel.com/t5/Intel-Software-Guard-Extensions/Reading-EXITINFO/m-p/1083418#M618</link>
      <description>&lt;P&gt;No, no page fault will the reported. Your laptop will only report exceptions described in the VECTOR Field Definition.&lt;/P&gt;

&lt;P&gt;In addition to the flow explained above, the sgx_urts.dll installs an exception handler before ECALLing into the enclave. If an exception happens while running within the enclave, the OS will search for registered exception handlers and will find what sgx_urts.dll has registered. When the sgx_urts.dll's handler gets control, ECALLs into the enclave again to execute the trusted exception handler. The enclave's handler access the information stored in the SSA and gives control to any exception handler the enclave might have registered. If the enclave handles the exception (EXCEPTION_CONTINUE_EXECUTION), sgx_urts.dll returns the same code to the OS, which then ERESUMEs and execution continues inside the enclave at the point where the exception (AEX) occurred. If the enclave doesn't handle the exception (EXCEPTION_EXECUTE_HANDLER) the OS will continue searching up the stack for a&amp;nbsp;handler and eventually will abort the application if no other is found.&lt;/P&gt;</description>
      <pubDate>Thu, 09 Jun 2016 13:41:23 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Software-Guard-Extensions/Reading-EXITINFO/m-p/1083418#M618</guid>
      <dc:creator>Juan_d_Intel</dc:creator>
      <dc:date>2016-06-09T13:41:23Z</dc:date>
    </item>
    <item>
      <title>Quote:Fabian N. wrote:</title>
      <link>https://community.intel.com/t5/Intel-Software-Guard-Extensions/Reading-EXITINFO/m-p/1083419#M619</link>
      <description>&lt;P&gt;&lt;/P&gt;&lt;BLOCKQUOTE&gt;Fabian N. wrote:&lt;BR /&gt;&lt;P&gt;&lt;/P&gt;

&lt;P&gt;That's exactly what I've been looking for.&lt;/P&gt;

&lt;P&gt;Just one thing: If I understand correctly, this handler will be called by ERESUME, when reenter the enclave after an interrupt or an exception. But ERESUME is called by untrusted application. Can the untrusted application bypass the exception handlers somehow?&lt;/P&gt;

&lt;P&gt;Fan&lt;/P&gt;

&lt;P&gt;&amp;nbsp;&lt;/P&gt;

&lt;P&gt;&lt;/P&gt;&lt;/BLOCKQUOTE&gt;&lt;P&gt;&lt;/P&gt;

&lt;P&gt;&amp;nbsp;&lt;/P&gt;

&lt;P&gt;Hi Fan, I have the same concern, since in general enclave program relies on (untrusted) OS to initialize the exception handling routines, isn't possible that malicious OS can re-direct the execution flow for some malicious purpose?&lt;/P&gt;

&lt;P&gt;On the other hand, it seems not possible for OS to directly steal secrets since registers within an Enclave has been "scrubbed" before AEX.&amp;nbsp;&lt;/P&gt;

&lt;P&gt;Please let me know if it makes sense to you, thanks.&lt;/P&gt;</description>
      <pubDate>Mon, 03 Jul 2017 01:38:36 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Software-Guard-Extensions/Reading-EXITINFO/m-p/1083419#M619</guid>
      <dc:creator>Irene__GP</dc:creator>
      <dc:date>2017-07-03T01:38:36Z</dc:date>
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