<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic https://community.intel.com/t5/Intel-Software-Guard-Extensions/Inquiry-About-Memory-Hardware-Require in Intel® Software Guard Extensions (Intel® SGX)</title>
    <link>https://community.intel.com/t5/Intel-Software-Guard-Extensions/https-community-intel-com-t5-Intel-Software-Guard-Extensions/m-p/1672433#M6326</link>
    <description>&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;Dear Intel Support Team,&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;I am writing to clarify a technical requirement outlined in your official SGX/TDX enabling documentation. Specifically, regarding the memory population rules stated below:&lt;/P&gt;&lt;BLOCKQUOTE&gt;&lt;P class=""&gt;&lt;EM&gt;“At minimum, all slot 0's of all Integrated Memory Controller (IMC) channels for all installed CPUs must be populated (i.e., 8 DIMMs per populated CPU socket, at least). DIMM population must be symmetric across IMCs.&lt;BR /&gt;The following figure shows possible populations per populated CPU with 8 or 16 DIMMs...”&lt;/EM&gt;&lt;/P&gt;&lt;/BLOCKQUOTE&gt;&lt;P class=""&gt;We seek clarification on the following points:&lt;/P&gt;&lt;OL&gt;&lt;LI&gt;&lt;P class=""&gt;DIMM Capacity Requirements:&lt;/P&gt;&lt;UL&gt;&lt;LI&gt;&lt;P class=""&gt;Does the requirement for populating 8 or 16 DIMMs impose&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;specific restrictions on DIMM capacity&amp;nbsp;(e.g., 16GB/32GB/64GB)?&lt;/P&gt;&lt;UL&gt;&lt;LI&gt;&lt;P class=""&gt;For example, is it permissible to use&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;mixed-capacity DIMMs&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;(e.g., 16GB and 32GB modules) across slots, provided the total count and symmetry requirements are met?&lt;/P&gt;&lt;/LI&gt;&lt;LI&gt;&lt;P class=""&gt;Or must all DIMMs be&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;identical in capacity?&lt;/P&gt;&lt;/LI&gt;&lt;/UL&gt;&lt;/LI&gt;&lt;/UL&gt;&lt;/LI&gt;&lt;LI&gt;&lt;P class=""&gt;Capacity Constraints (if applicable):&lt;/P&gt;&lt;UL&gt;&lt;LI&gt;&lt;P class=""&gt;If capacity restrictions exist, are there&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;minimum capacity thresholds&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;or&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;capacity combination rules&amp;nbsp;(e.g., per-DIMM minimum capacity, channel-level uniformity)?&lt;/P&gt;&lt;/LI&gt;&lt;/UL&gt;&lt;/LI&gt;&lt;/OL&gt;&lt;P class=""&gt;This clarification is critical for our hardware selection in multi-CPU server configurations. Your detailed guidance would be greatly appreciated.&lt;/P&gt;&lt;P class=""&gt;Thank you for your support!&lt;/P&gt;&lt;/DIV&gt;&lt;/DIV&gt;</description>
    <pubDate>Wed, 05 Mar 2025 08:44:24 GMT</pubDate>
    <dc:creator>Chancie</dc:creator>
    <dc:date>2025-03-05T08:44:24Z</dc:date>
    <item>
      <title>https://community.intel.com/t5/Intel-Software-Guard-Extensions/Inquiry-About-Memory-Hardware-Require</title>
      <link>https://community.intel.com/t5/Intel-Software-Guard-Extensions/https-community-intel-com-t5-Intel-Software-Guard-Extensions/m-p/1672433#M6326</link>
      <description>&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;Dear Intel Support Team,&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;I am writing to clarify a technical requirement outlined in your official SGX/TDX enabling documentation. Specifically, regarding the memory population rules stated below:&lt;/P&gt;&lt;BLOCKQUOTE&gt;&lt;P class=""&gt;&lt;EM&gt;“At minimum, all slot 0's of all Integrated Memory Controller (IMC) channels for all installed CPUs must be populated (i.e., 8 DIMMs per populated CPU socket, at least). DIMM population must be symmetric across IMCs.&lt;BR /&gt;The following figure shows possible populations per populated CPU with 8 or 16 DIMMs...”&lt;/EM&gt;&lt;/P&gt;&lt;/BLOCKQUOTE&gt;&lt;P class=""&gt;We seek clarification on the following points:&lt;/P&gt;&lt;OL&gt;&lt;LI&gt;&lt;P class=""&gt;DIMM Capacity Requirements:&lt;/P&gt;&lt;UL&gt;&lt;LI&gt;&lt;P class=""&gt;Does the requirement for populating 8 or 16 DIMMs impose&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;specific restrictions on DIMM capacity&amp;nbsp;(e.g., 16GB/32GB/64GB)?&lt;/P&gt;&lt;UL&gt;&lt;LI&gt;&lt;P class=""&gt;For example, is it permissible to use&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;mixed-capacity DIMMs&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;(e.g., 16GB and 32GB modules) across slots, provided the total count and symmetry requirements are met?&lt;/P&gt;&lt;/LI&gt;&lt;LI&gt;&lt;P class=""&gt;Or must all DIMMs be&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;identical in capacity?&lt;/P&gt;&lt;/LI&gt;&lt;/UL&gt;&lt;/LI&gt;&lt;/UL&gt;&lt;/LI&gt;&lt;LI&gt;&lt;P class=""&gt;Capacity Constraints (if applicable):&lt;/P&gt;&lt;UL&gt;&lt;LI&gt;&lt;P class=""&gt;If capacity restrictions exist, are there&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;minimum capacity thresholds&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;or&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;capacity combination rules&amp;nbsp;(e.g., per-DIMM minimum capacity, channel-level uniformity)?&lt;/P&gt;&lt;/LI&gt;&lt;/UL&gt;&lt;/LI&gt;&lt;/OL&gt;&lt;P class=""&gt;This clarification is critical for our hardware selection in multi-CPU server configurations. Your detailed guidance would be greatly appreciated.&lt;/P&gt;&lt;P class=""&gt;Thank you for your support!&lt;/P&gt;&lt;/DIV&gt;&lt;/DIV&gt;</description>
      <pubDate>Wed, 05 Mar 2025 08:44:24 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Software-Guard-Extensions/https-community-intel-com-t5-Intel-Software-Guard-Extensions/m-p/1672433#M6326</guid>
      <dc:creator>Chancie</dc:creator>
      <dc:date>2025-03-05T08:44:24Z</dc:date>
    </item>
    <item>
      <title>Re: https://community.intel.com/t5/Intel-Software-Guard-Extensions/Inquiry-About-Memory-Hardware-Req</title>
      <link>https://community.intel.com/t5/Intel-Software-Guard-Extensions/https-community-intel-com-t5-Intel-Software-Guard-Extensions/m-p/1672475#M6330</link>
      <description>&lt;P&gt;&lt;SPAN&gt;Duplicate of&amp;nbsp;&lt;/SPAN&gt;&lt;A class="sub_section_element_selectors" href="https://community.intel.com/t5/Intel-Software-Guard-Extensions/Inquiry-About-Memory-Hardware-Requirements-for-Enabling-Intel/m-p/1671213#M6321" target="_self"&gt;Thread 1671213&lt;/A&gt;&lt;SPAN&gt;. Closing&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Wed, 05 Mar 2025 10:44:47 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Software-Guard-Extensions/https-community-intel-com-t5-Intel-Software-Guard-Extensions/m-p/1672475#M6330</guid>
      <dc:creator>Benny_Intel</dc:creator>
      <dc:date>2025-03-05T10:44:47Z</dc:date>
    </item>
  </channel>
</rss>

