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    <title>topic HOW to get the L1,L2 Cache Miss of an intel i5 Sandy Bridge in Software Tuning, Performance Optimization &amp; Platform Monitoring</title>
    <link>https://community.intel.com/t5/Software-Tuning-Performance/HOW-to-get-the-L1-L2-Cache-Miss-of-an-intel-i5-Sandy-Bridge/m-p/822531#M1020</link>
    <description>Hello,&lt;DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;I am working with Vtune Amplifier XE it works fine so far, but with the i5 Sandy Bridge CPU(i5-2400)&lt;SPAN style="font-size: xx-small;"&gt;&lt;SPAN style="-webkit-border-horizontal-spacing: 2px; -webkit-border-vertical-spacing: 2px;"&gt;i have some problem.&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN style="font-size: xx-small;"&gt;&lt;SPAN style="-webkit-border-horizontal-spacing: 2px; -webkit-border-vertical-spacing: 2px;"&gt;&lt;BR /&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN style="font-size: xx-small;"&gt;&lt;SPAN style="-webkit-border-horizontal-spacing: 2px; -webkit-border-vertical-spacing: 2px;"&gt;1. How can i count the sum of L1 and L2 misses ?&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN style="font-size: xx-small;"&gt;&lt;SPAN style="-webkit-border-horizontal-spacing: 2px; -webkit-border-vertical-spacing: 2px;"&gt;&lt;SPAN style="white-space: pre;"&gt;	&lt;/SPAN&gt;I cannot find any event for it!&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN style="font-size: xx-small;"&gt;&lt;SPAN style="-webkit-border-horizontal-spacing: 2px; -webkit-border-vertical-spacing: 2px;"&gt;2. Are there some formulas to calculated it?&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN style="font-size: xx-small;"&gt;&lt;SPAN style="-webkit-border-horizontal-spacing: 2px; -webkit-border-vertical-spacing: 2px;"&gt;&lt;BR /&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN style="font-size: xx-small;"&gt;&lt;SPAN style="-webkit-border-horizontal-spacing: 2px; -webkit-border-vertical-spacing: 2px;"&gt;Can you please help me?&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN style="font-size: xx-small;"&gt;&lt;SPAN style="-webkit-border-horizontal-spacing: 2px; -webkit-border-vertical-spacing: 2px;"&gt;&lt;BR /&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN style="font-size: xx-small;"&gt;&lt;SPAN style="-webkit-border-horizontal-spacing: 2px; -webkit-border-vertical-spacing: 2px;"&gt;&lt;BR /&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN style="font-size: xx-small;"&gt;&lt;SPAN style="-webkit-border-horizontal-spacing: 2px; -webkit-border-vertical-spacing: 2px;"&gt;Regards&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN style="font-size: xx-small;"&gt;&lt;SPAN style="-webkit-border-horizontal-spacing: 2px; -webkit-border-vertical-spacing: 2px;"&gt;&lt;BR /&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN style="font-size: xx-small;"&gt;&lt;SPAN style="-webkit-border-horizontal-spacing: 2px; -webkit-border-vertical-spacing: 2px;"&gt;Andr&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN style="font-size: xx-small;"&gt;&lt;SPAN style="-webkit-border-horizontal-spacing: 2px; -webkit-border-vertical-spacing: 2px;"&gt;&lt;BR /&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN style="font-size: xx-small;"&gt;&lt;SPAN style="-webkit-border-horizontal-spacing: 2px; -webkit-border-vertical-spacing: 2px;"&gt;&lt;BR /&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN style="font-size: xx-small;"&gt;&lt;SPAN style="-webkit-border-horizontal-spacing: 2px; -webkit-border-vertical-spacing: 2px;"&gt;&lt;BR /&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/DIV&gt;</description>
    <pubDate>Thu, 26 Jan 2012 19:21:16 GMT</pubDate>
    <dc:creator>eandy</dc:creator>
    <dc:date>2012-01-26T19:21:16Z</dc:date>
    <item>
      <title>HOW to get the L1,L2 Cache Miss of an intel i5 Sandy Bridge</title>
      <link>https://community.intel.com/t5/Software-Tuning-Performance/HOW-to-get-the-L1-L2-Cache-Miss-of-an-intel-i5-Sandy-Bridge/m-p/822531#M1020</link>
      <description>Hello,&lt;DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;I am working with Vtune Amplifier XE it works fine so far, but with the i5 Sandy Bridge CPU(i5-2400)&lt;SPAN style="font-size: xx-small;"&gt;&lt;SPAN style="-webkit-border-horizontal-spacing: 2px; -webkit-border-vertical-spacing: 2px;"&gt;i have some problem.&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN style="font-size: xx-small;"&gt;&lt;SPAN style="-webkit-border-horizontal-spacing: 2px; -webkit-border-vertical-spacing: 2px;"&gt;&lt;BR /&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN style="font-size: xx-small;"&gt;&lt;SPAN style="-webkit-border-horizontal-spacing: 2px; -webkit-border-vertical-spacing: 2px;"&gt;1. How can i count the sum of L1 and L2 misses ?&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN style="font-size: xx-small;"&gt;&lt;SPAN style="-webkit-border-horizontal-spacing: 2px; -webkit-border-vertical-spacing: 2px;"&gt;&lt;SPAN style="white-space: pre;"&gt;	&lt;/SPAN&gt;I cannot find any event for it!&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN style="font-size: xx-small;"&gt;&lt;SPAN style="-webkit-border-horizontal-spacing: 2px; -webkit-border-vertical-spacing: 2px;"&gt;2. Are there some formulas to calculated it?&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN style="font-size: xx-small;"&gt;&lt;SPAN style="-webkit-border-horizontal-spacing: 2px; -webkit-border-vertical-spacing: 2px;"&gt;&lt;BR /&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN style="font-size: xx-small;"&gt;&lt;SPAN style="-webkit-border-horizontal-spacing: 2px; -webkit-border-vertical-spacing: 2px;"&gt;Can you please help me?&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN style="font-size: xx-small;"&gt;&lt;SPAN style="-webkit-border-horizontal-spacing: 2px; -webkit-border-vertical-spacing: 2px;"&gt;&lt;BR /&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN style="font-size: xx-small;"&gt;&lt;SPAN style="-webkit-border-horizontal-spacing: 2px; -webkit-border-vertical-spacing: 2px;"&gt;&lt;BR /&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN style="font-size: xx-small;"&gt;&lt;SPAN style="-webkit-border-horizontal-spacing: 2px; -webkit-border-vertical-spacing: 2px;"&gt;Regards&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN style="font-size: xx-small;"&gt;&lt;SPAN style="-webkit-border-horizontal-spacing: 2px; -webkit-border-vertical-spacing: 2px;"&gt;&lt;BR /&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN style="font-size: xx-small;"&gt;&lt;SPAN style="-webkit-border-horizontal-spacing: 2px; -webkit-border-vertical-spacing: 2px;"&gt;Andr&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN style="font-size: xx-small;"&gt;&lt;SPAN style="-webkit-border-horizontal-spacing: 2px; -webkit-border-vertical-spacing: 2px;"&gt;&lt;BR /&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN style="font-size: xx-small;"&gt;&lt;SPAN style="-webkit-border-horizontal-spacing: 2px; -webkit-border-vertical-spacing: 2px;"&gt;&lt;BR /&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN style="font-size: xx-small;"&gt;&lt;SPAN style="-webkit-border-horizontal-spacing: 2px; -webkit-border-vertical-spacing: 2px;"&gt;&lt;BR /&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/DIV&gt;</description>
      <pubDate>Thu, 26 Jan 2012 19:21:16 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Tuning-Performance/HOW-to-get-the-L1-L2-Cache-Miss-of-an-intel-i5-Sandy-Bridge/m-p/822531#M1020</guid>
      <dc:creator>eandy</dc:creator>
      <dc:date>2012-01-26T19:21:16Z</dc:date>
    </item>
    <item>
      <title>HOW to get the L1,L2 Cache Miss of an intel i5 Sandy Bridge</title>
      <link>https://community.intel.com/t5/Software-Tuning-Performance/HOW-to-get-the-L1-L2-Cache-Miss-of-an-intel-i5-Sandy-Bridge/m-p/822532#M1021</link>
      <description>Hello Andre,&lt;BR /&gt;You can count L1 load hits and L1 load misses with:&lt;BR /&gt;&lt;P&gt;MEM_UOPS_RETIRED.ALL_LOADS&lt;BR /&gt;MEM_LOAD_UOPS_RETIRED.L1_HIT&lt;BR /&gt;&lt;BR /&gt;Then you can compute:&lt;BR /&gt;%L1D_load_hit = 100.0*MEM_LOAD_UOPS_RETIRED.L1_HIT / MEM_UOPS_RETIRED.ALL_LOADS&lt;BR /&gt;and&lt;BR /&gt;%L1D_load_miss= 100.0*(MEM_UOPS_RETIRED.ALL_LOADS - MEM_LOAD_UOPS_RETIRED.L1_HIT) / MEM_UOPS_RETIRED.ALL_LOADS&lt;BR /&gt;&lt;BR /&gt;For the L2 load hit and miss you can use:&lt;BR /&gt;L2_RQSTS.DEMAND_DATA_RD_HIT&lt;BR /&gt;L2_RQSTS.ALL_DEMAND_DATA_RD&lt;BR /&gt;&lt;BR /&gt;Then you can compute:&lt;BR /&gt;%L2_demand_rd_hit = 100.0 * L2_RQSTS.DEMAND_DATA_RD_HIT / L2_RQSTS.ALL_DEMAND_DATA_RD&lt;BR /&gt;%L2_demand_rd_miss = 100.0 * (L2_RQSTS.ALL_DEMAND_DATA_RD - L2_RQSTS.DEMAND_DATA_RD_HIT) / L2_RQSTS.ALL_DEMAND_DATA_RD&lt;BR /&gt;&lt;BR /&gt;I hope this helps,&lt;BR /&gt;Pat&lt;/P&gt;</description>
      <pubDate>Sun, 29 Jan 2012 23:58:15 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Tuning-Performance/HOW-to-get-the-L1-L2-Cache-Miss-of-an-intel-i5-Sandy-Bridge/m-p/822532#M1021</guid>
      <dc:creator>Patrick_F_Intel1</dc:creator>
      <dc:date>2012-01-29T23:58:15Z</dc:date>
    </item>
    <item>
      <title>HOW to get the L1,L2 Cache Miss of an intel i5 Sandy Bridge</title>
      <link>https://community.intel.com/t5/Software-Tuning-Performance/HOW-to-get-the-L1-L2-Cache-Miss-of-an-intel-i5-Sandy-Bridge/m-p/822533#M1022</link>
      <description>Andre,&lt;BR /&gt;I have given an answer specific to Intel VTune Amplifier XE and the events it can count back on your first thread here: &lt;A href="http://software.intel.com/en-us/forums/showthread.php?t=102467"&gt;&lt;/A&gt;&lt;A href="http://software.intel.com/en-us/forums/showthread.php?t=102467" target="_blank"&gt;http://software.intel.com/en-us/forums/showthread.php?t=102467&lt;/A&gt;&lt;BR /&gt;It also gives instructions on how to find and use the events in VTune.&lt;BR /&gt;Thanks,&lt;BR /&gt;Shannon&lt;BR /&gt;</description>
      <pubDate>Fri, 03 Feb 2012 19:07:38 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Tuning-Performance/HOW-to-get-the-L1-L2-Cache-Miss-of-an-intel-i5-Sandy-Bridge/m-p/822533#M1022</guid>
      <dc:creator>Shannon_C_Intel</dc:creator>
      <dc:date>2012-02-03T19:07:38Z</dc:date>
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