https://community.intel.com/t5/Software-Tuning-Performance/Clks-busy-with-Page-Miss-Handler-on-PMC-0x08-and-0x49/m-p/828873#M1085 Hi,<DIV><SPAN style="white-space: pre;"> </SPAN>I'm measuring average page miss latency using PMCs 0x08 and 0x49. The documentation of these is here:</DIV><DIV></DIV><DIV><A href="http://software.intel.com/sites/products/documentation/hpc/amplifierxe/en-us/lin/ug_docs/reference/index.htm#snb/events/about_front_end_performance_tuning_events.html">http://software.intel.com/sites/products/documentation/hpc/amplifierxe/en-us/lin/ug_docs/reference/index.htm#snb/events/about_front_end_performance_tuning_events.html</A></DIV><DIV></DIV><DIV><A href="http://software.intel.com/sites/products/documentation/hpc/amplifierxe/en-us/lin/ug_docs/reference/index.htm#snb/events/about_front_end_performance_tuning_events.html">http://software.intel.com/sites/products/documentation/hpc/amplifierxe/en-us/lin/ug_docs/reference/index.htm#snb/events/about_front_end_performance_tuning_events.html</A></DIV><DIV></DIV><DIV>My question is is the cycles which the PMH is busy in PMC 0x08 due to only those generated by loads?</DIV><DIV></DIV><DIV>My next question is the counterpart for PMC 0x49, do the cycles counted there while the PMH is busy pertain only to stores?</DIV><DIV></DIV><DIV>It's vague at present, implying its for both, but all other unit masks measure only counts generated by their respective memory operation (load or store depending upon the PMC).</DIV><DIV></DIV><DIV>Thanks for any clarification</DIV><DIV></DIV><DIV>perfwise</DIV> Sat, 17 Sep 2011 03:00:06 GMT perfwise 2011-09-17T03:00:06Z https://community.intel.com/t5/Software-Tuning-Performance/Clks-busy-with-Page-Miss-Handler-on-PMC-0x08-and-0x49/m-p/828873#M1085 Hi,<DIV><SPAN style="white-space: pre;"> </SPAN>I'm measuring average page miss latency using PMCs 0x08 and 0x49. The documentation of these is here:</DIV><DIV></DIV><DIV><A href="http://software.intel.com/sites/products/documentation/hpc/amplifierxe/en-us/lin/ug_docs/reference/index.htm#snb/events/about_front_end_performance_tuning_events.html">http://software.intel.com/sites/products/documentation/hpc/amplifierxe/en-us/lin/ug_docs/reference/index.htm#snb/events/about_front_end_performance_tuning_events.html</A></DIV><DIV></DIV><DIV><A href="http://software.intel.com/sites/products/documentation/hpc/amplifierxe/en-us/lin/ug_docs/reference/index.htm#snb/events/about_front_end_performance_tuning_events.html">http://software.intel.com/sites/products/documentation/hpc/amplifierxe/en-us/lin/ug_docs/reference/index.htm#snb/events/about_front_end_performance_tuning_events.html</A></DIV><DIV></DIV><DIV>My question is is the cycles which the PMH is busy in PMC 0x08 due to only those generated by loads?</DIV><DIV></DIV><DIV>My next question is the counterpart for PMC 0x49, do the cycles counted there while the PMH is busy pertain only to stores?</DIV><DIV></DIV><DIV>It's vague at present, implying its for both, but all other unit masks measure only counts generated by their respective memory operation (load or store depending upon the PMC).</DIV><DIV></DIV><DIV>Thanks for any clarification</DIV><DIV></DIV><DIV>perfwise</DIV> Sat, 17 Sep 2011 03:00:06 GMT https://community.intel.com/t5/Software-Tuning-Performance/Clks-busy-with-Page-Miss-Handler-on-PMC-0x08-and-0x49/m-p/828873#M1085 perfwise 2011-09-17T03:00:06Z https://community.intel.com/t5/Software-Tuning-Performance/Clks-busy-with-Page-Miss-Handler-on-PMC-0x08-and-0x49/m-p/828874#M1086 Hello Perfwise,<BR />Yes, DTLB_LOAD_MISSES.* (PMC 0x8) is just for loads.<BR />And DTLB_STORE_MISSES.* (PMC 0x49) is just for stores.<BR />Pat Tue, 20 Sep 2011 22:13:48 GMT https://community.intel.com/t5/Software-Tuning-Performance/Clks-busy-with-Page-Miss-Handler-on-PMC-0x08-and-0x49/m-p/828874#M1086 Patrick_F_Intel1 2011-09-20T22:13:48Z