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    <title>topic Measuring L2 -&amp;gt; L1 Fill latency.. in Software Tuning, Performance Optimization &amp; Platform Monitoring</title>
    <link>https://community.intel.com/t5/Software-Tuning-Performance/Measuring-L2-gt-L1-Fill-latency/m-p/830079#M1096</link>
    <description>Hello perfwise,&lt;BR /&gt;&lt;P&gt;PMC 0x48, umask 0x1 (L1D_PEND_MISS.PENDING) incrementsthe number of outstanding L1D misses every cycle.&lt;BR /&gt;The counting probably starts as soon as an L1D miss occurs and before a buffer is allocated for the miss. &lt;BR /&gt;The L1Dmiss might require a trip to L2 or L3 or memory. I suspect that it counts bothcacheable and uncacheable memory accesses.&lt;BR /&gt;L1D_PEND_MISS contains an unknown mix of types of misses.&lt;BR /&gt;So you can't use it to compute an L2-&amp;gt;L1 miss latency.&lt;BR /&gt;Pat&lt;/P&gt;</description>
    <pubDate>Thu, 15 Sep 2011 13:12:29 GMT</pubDate>
    <dc:creator>Patrick_F_Intel1</dc:creator>
    <dc:date>2011-09-15T13:12:29Z</dc:date>
    <item>
      <title>Measuring L2 -&gt; L1 Fill latency..</title>
      <link>https://community.intel.com/t5/Software-Tuning-Performance/Measuring-L2-gt-L1-Fill-latency/m-p/830078#M1095</link>
      <description>I am trying to measure the L2 -&amp;gt; L1 Fill latency. &lt;DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;I'm using PMC 0x48 umask=0x01. This increments each cycle the number of Line Fill Buffers currently allocated, right?&lt;/DIV&gt;&lt;DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;If I also tabulate the number of allocations in the L1D (PMC 51 umask=0x01):&lt;/DIV&gt;&lt;DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;lt;# cycles a fill takes from L2 -&amp;gt; L1&amp;gt; =(# active LFB per instruction) / (# L1D allocations made per instruction)&lt;/DIV&gt;&lt;DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;Is this correct?&lt;/DIV&gt;&lt;DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;perfwise&lt;/DIV&gt;</description>
      <pubDate>Thu, 15 Sep 2011 01:17:27 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Tuning-Performance/Measuring-L2-gt-L1-Fill-latency/m-p/830078#M1095</guid>
      <dc:creator>perfwise</dc:creator>
      <dc:date>2011-09-15T01:17:27Z</dc:date>
    </item>
    <item>
      <title>Measuring L2 -&gt; L1 Fill latency..</title>
      <link>https://community.intel.com/t5/Software-Tuning-Performance/Measuring-L2-gt-L1-Fill-latency/m-p/830079#M1096</link>
      <description>Hello perfwise,&lt;BR /&gt;&lt;P&gt;PMC 0x48, umask 0x1 (L1D_PEND_MISS.PENDING) incrementsthe number of outstanding L1D misses every cycle.&lt;BR /&gt;The counting probably starts as soon as an L1D miss occurs and before a buffer is allocated for the miss. &lt;BR /&gt;The L1Dmiss might require a trip to L2 or L3 or memory. I suspect that it counts bothcacheable and uncacheable memory accesses.&lt;BR /&gt;L1D_PEND_MISS contains an unknown mix of types of misses.&lt;BR /&gt;So you can't use it to compute an L2-&amp;gt;L1 miss latency.&lt;BR /&gt;Pat&lt;/P&gt;</description>
      <pubDate>Thu, 15 Sep 2011 13:12:29 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Tuning-Performance/Measuring-L2-gt-L1-Fill-latency/m-p/830079#M1096</guid>
      <dc:creator>Patrick_F_Intel1</dc:creator>
      <dc:date>2011-09-15T13:12:29Z</dc:date>
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