topic Here is update... in Software Tuning, Performance Optimization & Platform Monitoring

Shared L1 data cache

Divino_C_ — Sat, 08 Jun 2013 21:41:25 GMT

Hello,

does Ivy Bridge (i7 3630qm) share L1 data cache between logical processors? How is it done?

thanks,
César.

>>...does Ivy Bridge (i7

SergeyKostrov — Sun, 09 Jun 2013 00:16:11 GMT

>>...does Ivy Bridge (i7 3630qm) share L1 data cache between logical processors?.. I don't think so and please take at ark.intel.com for technical details. When your CPU model is displayed a datasheet with additional technical information has to be in a right part of the webpage. For example, I have: Intel Core i7-3840QM ( Ivy Bridge / 4 cores / 8 logical CPUs / ark.intel.com/compare/70846 ) and these are data for all cache lines: Size of L3 Cache = 8MB ( shared between all cores for data & instructions ) Size of L2 Cache = 1MB ( 256KB per core / shared for data & instructions ) Size of L1 Cache = 256KB ( 32KB per core for data & 32KB per core for instructions )

It is not stated explicitly

Bernard — Sun, 09 Jun 2013 05:17:10 GMT

It is not stated explicitly in Intel documentation.

Btw ISM on page 580 table 3-17 provides some info related to thread starter question, here is a short excerpt from this table :Bits 25-14: Maximum number of addressable IDs for logical processors sharing this cache**, ***

Here is update...

SergeyKostrov — Sun, 09 Jun 2013 05:37:19 GMT

Here is update... L2 and L1 cache lines are shared between two Logical Processors, and L3 cache line is shared between all Logical Processors. Take a look at a Figure 2-8. Intel Core i7 Processor in Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 1: Basic Architecture on a page 45.

And one more thing: L2 and L1

SergeyKostrov — Sun, 09 Jun 2013 05:41:03 GMT

And one more thing: L2 and L1 cache lines are Not shared between Cores.

Thanks for the info.It seems

Bernard — Sun, 09 Jun 2013 06:09:31 GMT

Thanks for the info.It seems that I started my search from wrong page:)

I'd like to correct my

SergeyKostrov — Mon, 10 Jun 2013 04:32:41 GMT

I'd like to correct my previous statement. >>>>...does Ivy Bridge (i7 3630qm) share L1 data cache between logical processors?.. >> >>I don't think so... L2 and L1 cache lines are shared between two Logical Processors and Not shared between all the rest Cores.