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    <title>topic Yes that's true.For exmaple in Software Tuning, Performance Optimization &amp; Platform Monitoring</title>
    <link>https://community.intel.com/t5/Software-Tuning-Performance/Reading-QPI-Routing-Table/m-p/924518#M1420</link>
    <description>&lt;P&gt;Yes that's true.For exmaple access to this feature can be available from SMM mode only.&lt;/P&gt;</description>
    <pubDate>Fri, 10 May 2013 12:36:22 GMT</pubDate>
    <dc:creator>Bernard</dc:creator>
    <dc:date>2013-05-10T12:36:22Z</dc:date>
    <item>
      <title>Reading QPI Routing Table</title>
      <link>https://community.intel.com/t5/Software-Tuning-Performance/Reading-QPI-Routing-Table/m-p/924509#M1411</link>
      <description>&lt;P&gt;Hi there!&lt;/P&gt;
&lt;P&gt;Is there a way to read out the QPI routing table of a processor? I'm looking for something similar to the "cpuid" instruction that can be used to query the hardware directly. Since I'm not working with either Linux, or Windows I cannot use already existing programs...&lt;/P&gt;
&lt;P&gt;Is there a way to get this information from the hardware? -&amp;nbsp; I guess this is done differently for different processors, at the moment I'm especially interested in the XEON 7500 Series...&lt;/P&gt;
&lt;P&gt;&lt;/P&gt;
&lt;P&gt;Thank's in advance for any input!&lt;/P&gt;
&lt;P&gt;Robert&lt;/P&gt;
&lt;P&gt;&lt;/P&gt;</description>
      <pubDate>Sun, 14 Oct 2012 10:07:18 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Tuning-Performance/Reading-QPI-Routing-Table/m-p/924509#M1411</guid>
      <dc:creator>robchip</dc:creator>
      <dc:date>2012-10-14T10:07:18Z</dc:date>
    </item>
    <item>
      <title>Hello Robchip,</title>
      <link>https://community.intel.com/t5/Software-Tuning-Performance/Reading-QPI-Routing-Table/m-p/924510#M1412</link>
      <description>Hello Robchip,
There is a way to do this but it is not published. 
The manual &lt;A href="http://www.intel.com/Assets/en_US/PDF/datasheet/323341.pdf" target="_blank"&gt;http://www.intel.com/Assets/en_US/PDF/datasheet/323341.pdf&lt;/A&gt; mentions an overview of how to do it in section 13.2.1.1 'System Discovery' but the detail is not sufficient to actually decode the routing tables.
It will probably take a lot of work to get the information public.
Why do you want the information?
Pat</description>
      <pubDate>Mon, 29 Oct 2012 14:28:53 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Tuning-Performance/Reading-QPI-Routing-Table/m-p/924510#M1412</guid>
      <dc:creator>Patrick_F_Intel1</dc:creator>
      <dc:date>2012-10-29T14:28:53Z</dc:date>
    </item>
    <item>
      <title>You can consult relevant to</title>
      <link>https://community.intel.com/t5/Software-Tuning-Performance/Reading-QPI-Routing-Table/m-p/924511#M1413</link>
      <description>You can consult relevant to QPI chipset specification.</description>
      <pubDate>Mon, 24 Dec 2012 07:46:59 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Tuning-Performance/Reading-QPI-Routing-Table/m-p/924511#M1413</guid>
      <dc:creator>Bernard</dc:creator>
      <dc:date>2012-12-24T07:46:59Z</dc:date>
    </item>
    <item>
      <title>Hi. </title>
      <link>https://community.intel.com/t5/Software-Tuning-Performance/Reading-QPI-Routing-Table/m-p/924512#M1414</link>
      <description>&lt;P&gt;Hi.&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Could you tell me how to access the control register for Routing Layer in QPI ??&lt;/P&gt;
&lt;P&gt;I want to modify RTA(Router Table Array) for research purpose.&lt;/P&gt;
&lt;P&gt;Now I'm using CentOS6, but I couldn't find any piece of codes and "base address" related with QPI.&lt;/P&gt;
&lt;P&gt;any hints?&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Thanks.&lt;/P&gt;
&lt;P&gt;&lt;/P&gt;</description>
      <pubDate>Thu, 09 May 2013 18:29:41 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Tuning-Performance/Reading-QPI-Routing-Table/m-p/924512#M1414</guid>
      <dc:creator>wonjun_s_</dc:creator>
      <dc:date>2013-05-09T18:29:41Z</dc:date>
    </item>
    <item>
      <title>I do not think that you can</title>
      <link>https://community.intel.com/t5/Software-Tuning-Performance/Reading-QPI-Routing-Table/m-p/924513#M1415</link>
      <description>&lt;P&gt;I suppose that the access is done by MSR address space.&lt;/P&gt;</description>
      <pubDate>Thu, 09 May 2013 18:47:00 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Tuning-Performance/Reading-QPI-Routing-Table/m-p/924513#M1415</guid>
      <dc:creator>Bernard</dc:creator>
      <dc:date>2013-05-09T18:47:00Z</dc:date>
    </item>
    <item>
      <title>thanks for reply. :-)</title>
      <link>https://community.intel.com/t5/Software-Tuning-Performance/Reading-QPI-Routing-Table/m-p/924514#M1416</link>
      <description>&lt;P&gt;thanks for reply. :-)&lt;/P&gt;
&lt;P&gt;as you said. I also think so.&lt;/P&gt;
&lt;P&gt;wrmsr(), rdmsr() may be used to control that.&lt;/P&gt;
&lt;P&gt;But what I want to know what is the base address (or offset) to access registers for Routing Layer&lt;/P&gt;</description>
      <pubDate>Thu, 09 May 2013 19:38:33 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Tuning-Performance/Reading-QPI-Routing-Table/m-p/924514#M1416</guid>
      <dc:creator>wonjun_s_</dc:creator>
      <dc:date>2013-05-09T19:38:33Z</dc:date>
    </item>
    <item>
      <title>Hello Wonjun,</title>
      <link>https://community.intel.com/t5/Software-Tuning-Performance/Reading-QPI-Routing-Table/m-p/924515#M1417</link>
      <description>&lt;P&gt;Hello Wonjun,&lt;/P&gt;
&lt;P&gt;As I mentioned in the other thread, this info has not been publicly disclosed.&lt;/P&gt;
&lt;P&gt;Pat&lt;/P&gt;</description>
      <pubDate>Thu, 09 May 2013 19:56:35 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Tuning-Performance/Reading-QPI-Routing-Table/m-p/924515#M1417</guid>
      <dc:creator>Patrick_F_Intel1</dc:creator>
      <dc:date>2013-05-09T19:56:35Z</dc:date>
    </item>
    <item>
      <title>Quote:wonjun s. wrote:</title>
      <link>https://community.intel.com/t5/Software-Tuning-Performance/Reading-QPI-Routing-Table/m-p/924516#M1418</link>
      <description>&lt;P&gt;&lt;/P&gt;&lt;BLOCKQUOTE&gt;wonjun s. wrote:&lt;BR /&gt;&lt;P&gt;&lt;/P&gt;
&lt;P&gt;thanks for reply. :-)&lt;/P&gt;
&lt;P&gt;as you said. I also think so.&lt;/P&gt;
&lt;P&gt;&lt;/P&gt;
&lt;P&gt;wrmsr(), rdmsr() may be used to control that.&lt;/P&gt;
&lt;P&gt;But what I want to know what is the base address (or offset) to access registers for Routing Layer&lt;/P&gt;
&lt;P&gt;&lt;/P&gt;&lt;/BLOCKQUOTE&gt;&lt;P&gt;&lt;/P&gt;
&lt;P&gt;An option of last resort will be hooking kernel debugger and try to locate MSR register with the help of kd.Not an easy task when the address is not available or disclosed.&lt;/P&gt;</description>
      <pubDate>Fri, 10 May 2013 05:10:45 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Tuning-Performance/Reading-QPI-Routing-Table/m-p/924516#M1418</guid>
      <dc:creator>Bernard</dc:creator>
      <dc:date>2013-05-10T05:10:45Z</dc:date>
    </item>
    <item>
      <title>Just to save the time of</title>
      <link>https://community.intel.com/t5/Software-Tuning-Performance/Reading-QPI-Routing-Table/m-p/924517#M1419</link>
      <description>&lt;P&gt;Just to save the time of anyone thinking of pursuing the kernel debugger route...I doubt that using the kernel debugger will be fruitful in this case.&lt;/P&gt;
&lt;P&gt;Pat&lt;/P&gt;</description>
      <pubDate>Fri, 10 May 2013 11:44:57 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Tuning-Performance/Reading-QPI-Routing-Table/m-p/924517#M1419</guid>
      <dc:creator>Patrick_F_Intel1</dc:creator>
      <dc:date>2013-05-10T11:44:57Z</dc:date>
    </item>
    <item>
      <title>Yes that's true.For exmaple</title>
      <link>https://community.intel.com/t5/Software-Tuning-Performance/Reading-QPI-Routing-Table/m-p/924518#M1420</link>
      <description>&lt;P&gt;Yes that's true.For exmaple access to this feature can be available from SMM mode only.&lt;/P&gt;</description>
      <pubDate>Fri, 10 May 2013 12:36:22 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Tuning-Performance/Reading-QPI-Routing-Table/m-p/924518#M1420</guid>
      <dc:creator>Bernard</dc:creator>
      <dc:date>2013-05-10T12:36:22Z</dc:date>
    </item>
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