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    <title>topic Passing some memory boundary values to 'prefetcht*' instruction in Software Tuning, Performance Optimization &amp; Platform Monitoring</title>
    <link>https://community.intel.com/t5/Software-Tuning-Performance/Passing-some-memory-boundary-values-to-prefetcht-instructions/m-p/771079#M209</link>
    <description>&lt;DIV id="tiny_quote"&gt;&lt;DIV style="margin-left: 2px; margin-right: 2px;"&gt;&lt;EM&gt;&amp;gt;&amp;gt;xor rax,rax&lt;BR /&gt;&amp;gt;&amp;gt;prefetcht0 [rax]&lt;BR /&gt;&amp;gt;&amp;gt;&lt;BR /&gt;&amp;gt;&amp;gt;I think the &lt;SPAN style="text-decoration: underline;"&gt;&lt;STRONG&gt;exceptions get squished&lt;/STRONG&gt;&lt;/SPAN&gt; (not delivered back to the app) but there is a penalty.&lt;BR /&gt;&lt;BR /&gt;&lt;/EM&gt; Hi Patrick, I simply would like to follow up. You mentioned some exceptions. Do you mean&lt;BR /&gt; some internal CPU exceptions, or some exceptions from anoperating system?&lt;BR /&gt;&lt;BR /&gt; Could provide a little bit more technicaldetails, please?&lt;BR /&gt;&lt;BR /&gt; Best regards,&lt;BR /&gt; Sergey&lt;/DIV&gt;&lt;/DIV&gt;</description>
    <pubDate>Sat, 14 Jan 2012 20:29:27 GMT</pubDate>
    <dc:creator>SergeyKostrov</dc:creator>
    <dc:date>2012-01-14T20:29:27Z</dc:date>
    <item>
      <title>Passing some memory boundary values to 'prefetcht*' instructions</title>
      <link>https://community.intel.com/t5/Software-Tuning-Performance/Passing-some-memory-boundary-values-to-prefetcht-instructions/m-p/771075#M205</link>
      <description>What happens if some memory boundary values, like &lt;STRONG&gt;0x00000000&lt;/STRONG&gt; or &lt;STRONG&gt;0xFFFFFFFF&lt;/STRONG&gt;, are passed to '&lt;STRONG&gt;prefetcht*&lt;/STRONG&gt;' instructions on a 32-bit platform?&lt;BR /&gt;&lt;BR /&gt;Here is an example:&lt;BR /&gt;&lt;BR /&gt; ...&lt;BR /&gt; &lt;STRONG&gt;_mm_prefetch&lt;/STRONG&gt;( 0xFFFFFFFF, _MM_HINT_T0);&lt;BR /&gt; ...&lt;BR /&gt;&lt;BR /&gt;Best regards,&lt;BR /&gt;Sergey&lt;BR /&gt;</description>
      <pubDate>Fri, 23 Dec 2011 14:04:12 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Tuning-Performance/Passing-some-memory-boundary-values-to-prefetcht-instructions/m-p/771075#M205</guid>
      <dc:creator>SergeyKostrov</dc:creator>
      <dc:date>2011-12-23T14:04:12Z</dc:date>
    </item>
    <item>
      <title>Passing some memory boundary values to 'prefetcht*' instruction</title>
      <link>https://community.intel.com/t5/Software-Tuning-Performance/Passing-some-memory-boundary-values-to-prefetcht-instructions/m-p/771076#M206</link>
      <description>Hello Sergey,&lt;BR /&gt;I did a quick test on 64bit windows platform andthe exceptions don't getdelivered back to my program.&lt;BR /&gt;I did a loop of:&lt;BR /&gt;xor rax,rax&lt;BR /&gt;prefetcht0 [rax]&lt;BR /&gt;&lt;BR /&gt;I think the exceptions get squished (not delivered back to the app) but there is a penalty.&lt;BR /&gt;The performance seems to be about equal to a trip to memory per reference on my "processor formerly codenamed Westmere"-based laptop.&lt;BR /&gt;I will check with others after the holidays.&lt;BR /&gt;Pat&lt;BR /&gt;</description>
      <pubDate>Fri, 23 Dec 2011 23:56:05 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Tuning-Performance/Passing-some-memory-boundary-values-to-prefetcht-instructions/m-p/771076#M206</guid>
      <dc:creator>Patrick_F_Intel1</dc:creator>
      <dc:date>2011-12-23T23:56:05Z</dc:date>
    </item>
    <item>
      <title>Passing some memory boundary values to 'prefetcht*' instruction</title>
      <link>https://community.intel.com/t5/Software-Tuning-Performance/Passing-some-memory-boundary-values-to-prefetcht-instructions/m-p/771077#M207</link>
      <description>&lt;DIV id="tiny_quote"&gt;&lt;DIV style="margin-left: 2px; margin-right: 2px;"&gt;Quoting &lt;A jquery1324687700343="53" rel="/en-us/services/profile/quick_profile.php?is_paid=&amp;amp;user_id=335837" href="https://community.intel.com/en-us/profile/335837/" class="basic"&gt;Patrick Fay (Intel)&lt;/A&gt;&lt;/DIV&gt;&lt;DIV style="background-color: #e5e5e5; margin-left: 2px; margin-right: 2px; border: 1px inset; padding: 5px;"&gt;&lt;I&gt;...&lt;BR /&gt;I will check with others after the holidays.&lt;BR /&gt;Pat&lt;BR /&gt;&lt;/I&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;P&gt;&lt;BR /&gt;Thank you, Patrick, and Merry Christmas!&lt;BR /&gt;&lt;BR /&gt;PS: It would be good to see more technical details later...&lt;/P&gt;</description>
      <pubDate>Sat, 24 Dec 2011 00:53:21 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Tuning-Performance/Passing-some-memory-boundary-values-to-prefetcht-instructions/m-p/771077#M207</guid>
      <dc:creator>SergeyKostrov</dc:creator>
      <dc:date>2011-12-24T00:53:21Z</dc:date>
    </item>
    <item>
      <title>Passing some memory boundary values to 'prefetcht*' instruction</title>
      <link>https://community.intel.com/t5/Software-Tuning-Performance/Passing-some-memory-boundary-values-to-prefetcht-instructions/m-p/771078#M208</link>
      <description>&lt;P&gt;Merry Christmas and happy holidays to you too!&lt;/P&gt;</description>
      <pubDate>Sat, 24 Dec 2011 01:14:34 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Tuning-Performance/Passing-some-memory-boundary-values-to-prefetcht-instructions/m-p/771078#M208</guid>
      <dc:creator>Patrick_F_Intel1</dc:creator>
      <dc:date>2011-12-24T01:14:34Z</dc:date>
    </item>
    <item>
      <title>Passing some memory boundary values to 'prefetcht*' instruction</title>
      <link>https://community.intel.com/t5/Software-Tuning-Performance/Passing-some-memory-boundary-values-to-prefetcht-instructions/m-p/771079#M209</link>
      <description>&lt;DIV id="tiny_quote"&gt;&lt;DIV style="margin-left: 2px; margin-right: 2px;"&gt;&lt;EM&gt;&amp;gt;&amp;gt;xor rax,rax&lt;BR /&gt;&amp;gt;&amp;gt;prefetcht0 [rax]&lt;BR /&gt;&amp;gt;&amp;gt;&lt;BR /&gt;&amp;gt;&amp;gt;I think the &lt;SPAN style="text-decoration: underline;"&gt;&lt;STRONG&gt;exceptions get squished&lt;/STRONG&gt;&lt;/SPAN&gt; (not delivered back to the app) but there is a penalty.&lt;BR /&gt;&lt;BR /&gt;&lt;/EM&gt; Hi Patrick, I simply would like to follow up. You mentioned some exceptions. Do you mean&lt;BR /&gt; some internal CPU exceptions, or some exceptions from anoperating system?&lt;BR /&gt;&lt;BR /&gt; Could provide a little bit more technicaldetails, please?&lt;BR /&gt;&lt;BR /&gt; Best regards,&lt;BR /&gt; Sergey&lt;/DIV&gt;&lt;/DIV&gt;</description>
      <pubDate>Sat, 14 Jan 2012 20:29:27 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Tuning-Performance/Passing-some-memory-boundary-values-to-prefetcht-instructions/m-p/771079#M209</guid>
      <dc:creator>SergeyKostrov</dc:creator>
      <dc:date>2012-01-14T20:29:27Z</dc:date>
    </item>
    <item>
      <title>Passing some memory boundary values to 'prefetcht*' instruction</title>
      <link>https://community.intel.com/t5/Software-Tuning-Performance/Passing-some-memory-boundary-values-to-prefetcht-instructions/m-p/771080#M210</link>
      <description>Hello Sergey,&lt;BR /&gt;Sorry for the delay.&lt;BR /&gt;&lt;BR /&gt;The prefetch* instructions will not raise an exception for an invalid address but there will be a slight performance penalty. &lt;BR /&gt;The penalty varies on existing processors, but it derives from the need to walk the page tables in order to determine that a given address is invalid. &lt;BR /&gt;Note that SDM instruction set reference does not list the #PF (invalid address) exception for the prefetch* instructions indicating that this instruction doesn't raise the #PF exception.&lt;BR /&gt;&lt;BR /&gt;I hope this helps,&lt;BR /&gt;Pat</description>
      <pubDate>Thu, 26 Jan 2012 00:09:40 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Tuning-Performance/Passing-some-memory-boundary-values-to-prefetcht-instructions/m-p/771080#M210</guid>
      <dc:creator>Patrick_F_Intel1</dc:creator>
      <dc:date>2012-01-26T00:09:40Z</dc:date>
    </item>
    <item>
      <title>Passing some memory boundary values to 'prefetcht*' instruction</title>
      <link>https://community.intel.com/t5/Software-Tuning-Performance/Passing-some-memory-boundary-values-to-prefetcht-instructions/m-p/771081#M211</link>
      <description>Just to add:&lt;BR /&gt;&lt;BR /&gt;This is because an invalid address will not be present in the TLB(Supfast bufferfor Vto P translation).&lt;BR /&gt;So, the TLB miss will cause the page-table walk and hence the penalty..</description>
      <pubDate>Wed, 01 Feb 2012 12:48:03 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Tuning-Performance/Passing-some-memory-boundary-values-to-prefetcht-instructions/m-p/771081#M211</guid>
      <dc:creator>k_sarnath</dc:creator>
      <dc:date>2012-02-01T12:48:03Z</dc:date>
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