<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Vid and Fid control, from Core 2 to Haswell in Software Tuning, Performance Optimization &amp; Platform Monitoring</title>
    <link>https://community.intel.com/t5/Software-Tuning-Performance/Vid-and-Fid-control-from-Core-2-to-Haswell/m-p/970823#M2789</link>
    <description>&lt;P&gt;Hi,&lt;/P&gt;
&lt;P&gt;Im a currently working on a way to reduce power consumption and related heat dissipation. A good way on Core 2 CPUs was to play with Fid and Vid.&lt;/P&gt;
&lt;P&gt;On linux, I load the msr module from the kernel : &lt;EM&gt;modprobe msr&lt;/EM&gt;&lt;/P&gt;
&lt;P&gt;And then I can affect Vid and Fid. On my Core 2 E8500, I was able to reduce power consuption by 15% without an impact on performances, by undervolting cpu for max frequency using for example :&lt;/P&gt;
&lt;P&gt;&lt;EM&gt;wrmsr -p 0 0x199 0x0223&lt;/EM&gt;&lt;/P&gt;
&lt;P&gt;And applying this value every 0.1s.&lt;/P&gt;
&lt;P&gt;etc.&lt;/P&gt;
&lt;P&gt;I am looking for a way to do the same on Nehalem/Westmer, Sandy Bridge/IvyBridge, and Haswell. However, I do not find any documentation to know if it's still possible on the Intel Xeon series (I am using an E5520 for testing), and what are the msr addresses to be used to know defaults Fid/Vid and to change on the fly currently used Fid/Vid.&lt;/P&gt;
&lt;P&gt;Is there a specific PDF or web page that regroups these informations ?&lt;/P&gt;
&lt;P&gt;&lt;/P&gt;
&lt;P&gt;With My best regards.&lt;/P&gt;</description>
    <pubDate>Wed, 07 Aug 2013 12:20:59 GMT</pubDate>
    <dc:creator>benoit_leveugle</dc:creator>
    <dc:date>2013-08-07T12:20:59Z</dc:date>
    <item>
      <title>Vid and Fid control, from Core 2 to Haswell</title>
      <link>https://community.intel.com/t5/Software-Tuning-Performance/Vid-and-Fid-control-from-Core-2-to-Haswell/m-p/970823#M2789</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;
&lt;P&gt;Im a currently working on a way to reduce power consumption and related heat dissipation. A good way on Core 2 CPUs was to play with Fid and Vid.&lt;/P&gt;
&lt;P&gt;On linux, I load the msr module from the kernel : &lt;EM&gt;modprobe msr&lt;/EM&gt;&lt;/P&gt;
&lt;P&gt;And then I can affect Vid and Fid. On my Core 2 E8500, I was able to reduce power consuption by 15% without an impact on performances, by undervolting cpu for max frequency using for example :&lt;/P&gt;
&lt;P&gt;&lt;EM&gt;wrmsr -p 0 0x199 0x0223&lt;/EM&gt;&lt;/P&gt;
&lt;P&gt;And applying this value every 0.1s.&lt;/P&gt;
&lt;P&gt;etc.&lt;/P&gt;
&lt;P&gt;I am looking for a way to do the same on Nehalem/Westmer, Sandy Bridge/IvyBridge, and Haswell. However, I do not find any documentation to know if it's still possible on the Intel Xeon series (I am using an E5520 for testing), and what are the msr addresses to be used to know defaults Fid/Vid and to change on the fly currently used Fid/Vid.&lt;/P&gt;
&lt;P&gt;Is there a specific PDF or web page that regroups these informations ?&lt;/P&gt;
&lt;P&gt;&lt;/P&gt;
&lt;P&gt;With My best regards.&lt;/P&gt;</description>
      <pubDate>Wed, 07 Aug 2013 12:20:59 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Tuning-Performance/Vid-and-Fid-control-from-Core-2-to-Haswell/m-p/970823#M2789</guid>
      <dc:creator>benoit_leveugle</dc:creator>
      <dc:date>2013-08-07T12:20:59Z</dc:date>
    </item>
    <item>
      <title>Hello benoit,</title>
      <link>https://community.intel.com/t5/Software-Tuning-Performance/Vid-and-Fid-control-from-Core-2-to-Haswell/m-p/970824#M2790</link>
      <description>&lt;P&gt;Hello benoit,&lt;/P&gt;
&lt;P&gt;The MSR addresses haven't changed. You can look in the SDM vol 3 (Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume (3A, 3B &amp;amp; 3C) System Programming Guide). In the june 2013 version, the MSRs are defined in chapter 35. The architectural MSRs (MSRs defined as "we going to support this MSR from chip x going forward") are defined in table 35-2. You'll see IA32_PERF_STATUS (MSR 0x198) and IA32_PERF_CTL (MSR 0x199).&lt;/P&gt;
&lt;P&gt;The low 2 bytes control the FID and VID but Intel has not made public the fields within the 2 bytes. You can pretty much figure them out by just inspecting IA32_PERF_STATUS but I think the fields somewhat between processors.&lt;/P&gt;
&lt;P&gt;Rather than reinvent the wheel, have you considered using the builtin linux power management facilities? Unless you are willing to dedicate your life to your utility, the builtin and/or available utilities (such as &lt;A href="https://wiki.debian.org/HowTo/CpuFrequencyScaling"&gt;https://wiki.debian.org/HowTo/CpuFrequencyScaling&lt;/A&gt;) will probably have many more features and already handle the many variations of a chip. And in any case, you can look at the source code of these utitlies and see how they do their work.&lt;/P&gt;
&lt;P&gt;Pat&lt;/P&gt;</description>
      <pubDate>Wed, 07 Aug 2013 12:51:09 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Tuning-Performance/Vid-and-Fid-control-from-Core-2-to-Haswell/m-p/970824#M2790</guid>
      <dc:creator>Patrick_F_Intel1</dc:creator>
      <dc:date>2013-08-07T12:51:09Z</dc:date>
    </item>
    <item>
      <title>Hello Patrick,</title>
      <link>https://community.intel.com/t5/Software-Tuning-Performance/Vid-and-Fid-control-from-Core-2-to-Haswell/m-p/970825#M2791</link>
      <description>&lt;P&gt;Hello Patrick,&lt;/P&gt;
&lt;P&gt;Thank you for these informations. In fact, I am aware of the cpufreq tool. I already use it to limit frequency when useful (laptop especially). However, I observed that most CPU are using more energy than needed. For example, when using my Core 2, when calculating at full frequency, I can reduce the CPU voltage from 1.25v to 1.0v with same performances and stability, but using less energy (tested with a Watt meter) and reducing CPU temperature (I get more than 10°C less !).&lt;/P&gt;
&lt;P&gt;The cpufreq tool is only dedicated to frequency scaling and do not play with voltages if I read right.&lt;/P&gt;
&lt;P&gt;So, I can re-use the same MSR to override CPU VID and FID. I will try it and keep you in touch.&lt;/P&gt;
&lt;P&gt;Ben&lt;/P&gt;</description>
      <pubDate>Wed, 07 Aug 2013 13:47:00 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Tuning-Performance/Vid-and-Fid-control-from-Core-2-to-Haswell/m-p/970825#M2791</guid>
      <dc:creator>benoit_leveugle</dc:creator>
      <dc:date>2013-08-07T13:47:00Z</dc:date>
    </item>
    <item>
      <title>I have strange results on the</title>
      <link>https://community.intel.com/t5/Software-Tuning-Performance/Vid-and-Fid-control-from-Core-2-to-Haswell/m-p/970826#M2792</link>
      <description>&lt;P&gt;I have strange results on the Nehalem.&lt;/P&gt;
&lt;P&gt;On the Core 2, I used the batch script :&lt;/P&gt;
&lt;P&gt;for MSR in 198 199 1A0; do for CPU in `sed -rn 's@^processor[\t]: ([0-9]+)$@\1@p' /proc/cpuinfo`; do echo -n "CPU${CPU} ${MSR}: "; sudo rdmsr -0 -X -p ${CPU} 0x${MSR}; done; done&lt;/P&gt;
&lt;P&gt;I obtained :&lt;/P&gt;
&lt;P&gt;CPU0 198: 0616492606000616&lt;BR /&gt; CPU1 198: 0616492606004926&lt;BR /&gt;CPU0 199: 0000000000000616&lt;BR /&gt;CPU1 199: 0000000000004926&lt;BR /&gt;CPU0 1A0: 0000004062972089&lt;BR /&gt;CPU1 1A0: 0000004062972089&lt;/P&gt;
&lt;P&gt;Which is all I need. On the Nehalem I got :&lt;/P&gt;
&lt;P&gt;CPU0 198: 0000000000000010&lt;BR /&gt;CPU1 198: 000000000000000C&lt;BR /&gt;CPU2 198: 000000000000000C&lt;BR /&gt;CPU3 198: 000000000000000C&lt;BR /&gt;CPU4 198: 0000000000000012&lt;BR /&gt;CPU5 198: 000000000000000C&lt;BR /&gt;CPU6 198: 000000000000000C&lt;BR /&gt;CPU7 198: 000000000000000C&lt;BR /&gt;CPU0 199: 000000000000000C&lt;BR /&gt;CPU1 199: 000000000000000C&lt;BR /&gt;CPU2 199: 000000000000000C&lt;BR /&gt;CPU3 199: 000000000000000C&lt;BR /&gt;CPU4 199: 000000000000000C&lt;BR /&gt;CPU5 199: 000000000000000C&lt;BR /&gt;CPU6 199: 000000000000000C&lt;BR /&gt;CPU7 199: 000000000000000C&lt;BR /&gt;CPU0 1A0: 0000000000850089&lt;BR /&gt;CPU1 1A0: 0000000000850089&lt;BR /&gt;CPU2 1A0: 0000000000850089&lt;BR /&gt;CPU3 1A0: 0000000000850089&lt;BR /&gt;CPU4 1A0: 0000000000850089&lt;BR /&gt;CPU5 1A0: 0000000000850089&lt;BR /&gt;CPU6 1A0: 0000000000850089&lt;BR /&gt;CPU7 1A0: 0000000000850089&lt;/P&gt;
&lt;P&gt;Few informations, but not that much. To be honest I still have not read the documentation your provided, and I now switch on this task. Do you have any idea why I got so few informations ?&lt;/P&gt;
&lt;P&gt;&lt;/P&gt;
&lt;P&gt;&lt;/P&gt;
&lt;P&gt;&lt;/P&gt;</description>
      <pubDate>Wed, 07 Aug 2013 14:59:30 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Tuning-Performance/Vid-and-Fid-control-from-Core-2-to-Haswell/m-p/970826#M2792</guid>
      <dc:creator>benoit_leveugle</dc:creator>
      <dc:date>2013-08-07T14:59:30Z</dc:date>
    </item>
    <item>
      <title>Hello Benoit, Sorry, I don't</title>
      <link>https://community.intel.com/t5/Software-Tuning-Performance/Vid-and-Fid-control-from-Core-2-to-Haswell/m-p/970827#M2793</link>
      <description>&lt;P&gt;Hello Benoit, Sorry, I don't have the time to debug your code.. Like I said, the folks writing cpufreq have probably spent many man-years on the code. Maybe someone else has the time. Pat&lt;/P&gt;</description>
      <pubDate>Wed, 07 Aug 2013 15:06:01 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Tuning-Performance/Vid-and-Fid-control-from-Core-2-to-Haswell/m-p/970827#M2793</guid>
      <dc:creator>Patrick_F_Intel1</dc:creator>
      <dc:date>2013-08-07T15:06:01Z</dc:date>
    </item>
  </channel>
</rss>

