<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Load Latency PEBS in Software Tuning, Performance Optimization &amp; Platform Monitoring</title>
    <link>https://community.intel.com/t5/Software-Tuning-Performance/Load-Latency-PEBS/m-p/973830#M2888</link>
    <description>&lt;P&gt;Hi,&lt;/P&gt;
&lt;P&gt;I was measuring the&amp;nbsp; load latencies in my core i5 2450 using PEBS + load latency feature of the PMU.&amp;nbsp; The document says , latency value is measured in core cycles from micro-operation (uop) dispatch to when data is globally observable (GO). I have the following queries&lt;/P&gt;
&lt;P&gt;1.&amp;nbsp; What is meant by 'when data is globally observable' ?&lt;BR /&gt;2.&amp;nbsp; The L1 latency is around 4-5 cycles.&amp;nbsp; But when I measure it using the PEBS, I get L1 hit latency values of even &amp;gt;100 cycles also.&amp;nbsp; ( It is a hit in dtlb/stlvb)&lt;/P&gt;
&lt;P&gt;Can some one give a clarification&lt;/P&gt;
&lt;P&gt;Thank you.&lt;/P&gt;
&lt;P&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;/P&gt;
&lt;P&gt;&lt;/P&gt;</description>
    <pubDate>Mon, 04 Nov 2013 06:36:35 GMT</pubDate>
    <dc:creator>Mohamed_Husain</dc:creator>
    <dc:date>2013-11-04T06:36:35Z</dc:date>
    <item>
      <title>Load Latency PEBS</title>
      <link>https://community.intel.com/t5/Software-Tuning-Performance/Load-Latency-PEBS/m-p/973830#M2888</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;
&lt;P&gt;I was measuring the&amp;nbsp; load latencies in my core i5 2450 using PEBS + load latency feature of the PMU.&amp;nbsp; The document says , latency value is measured in core cycles from micro-operation (uop) dispatch to when data is globally observable (GO). I have the following queries&lt;/P&gt;
&lt;P&gt;1.&amp;nbsp; What is meant by 'when data is globally observable' ?&lt;BR /&gt;2.&amp;nbsp; The L1 latency is around 4-5 cycles.&amp;nbsp; But when I measure it using the PEBS, I get L1 hit latency values of even &amp;gt;100 cycles also.&amp;nbsp; ( It is a hit in dtlb/stlvb)&lt;/P&gt;
&lt;P&gt;Can some one give a clarification&lt;/P&gt;
&lt;P&gt;Thank you.&lt;/P&gt;
&lt;P&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;/P&gt;
&lt;P&gt;&lt;/P&gt;</description>
      <pubDate>Mon, 04 Nov 2013 06:36:35 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Tuning-Performance/Load-Latency-PEBS/m-p/973830#M2888</guid>
      <dc:creator>Mohamed_Husain</dc:creator>
      <dc:date>2013-11-04T06:36:35Z</dc:date>
    </item>
    <item>
      <title>1) I think that "Globally</title>
      <link>https://community.intel.com/t5/Software-Tuning-Performance/Load-Latency-PEBS/m-p/973831#M2889</link>
      <description>&lt;P&gt;1) I think that "Globally Observable" might be related to data beign seen and accessed by the software(registers and or memory location).&lt;/P&gt;
&lt;P&gt;&lt;/P&gt;</description>
      <pubDate>Mon, 04 Nov 2013 07:51:44 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Tuning-Performance/Load-Latency-PEBS/m-p/973831#M2889</guid>
      <dc:creator>Bernard</dc:creator>
      <dc:date>2013-11-04T07:51:44Z</dc:date>
    </item>
  </channel>
</rss>

