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    <title>topic Hello Alexander, in Software Tuning, Performance Optimization &amp; Platform Monitoring</title>
    <link>https://community.intel.com/t5/Software-Tuning-Performance/Collect-TOR-INSERTS-OPCODE-for-two-opcodes-simultaneously/m-p/975306#M2924</link>
    <description>&lt;P&gt;Hello Alexander,&lt;/P&gt;
&lt;P&gt;I think you've got it right. Note that the&amp;nbsp;opcodes&amp;nbsp;0x194 and 0x19c look like just PCIe writes into the LLC (if I understand correctly).&amp;nbsp; It looks like the size in bytes for the 0x194 opcode is assumed to be 1 byte. That sounds like a swag to me. Usually when I see&amp;nbsp;events like this I think: one event is showing a full cache line transfer and another showing a "not sure what the size is but, it is probably&amp;nbsp;not cached, and&amp;nbsp;it is less than 64 bytes, might be 1, 2, 4, 8 or 16 bytes". Hopefully the the 0x194 counts are small so the fuzziness doesn't mess you up.&lt;/P&gt;
&lt;P&gt;Pat&lt;/P&gt;</description>
    <pubDate>Thu, 30 May 2013 13:57:34 GMT</pubDate>
    <dc:creator>Patrick_F_Intel1</dc:creator>
    <dc:date>2013-05-30T13:57:34Z</dc:date>
    <item>
      <title>Collect TOR_INSERTS.OPCODE for two opcodes simultaneously</title>
      <link>https://community.intel.com/t5/Software-Tuning-Performance/Collect-TOR-INSERTS-OPCODE-for-two-opcodes-simultaneously/m-p/975305#M2923</link>
      <description>&lt;P&gt;Hello.&lt;/P&gt;
&lt;P&gt;It might be a question with obvious answer. But I just want to confirm that my understanding is correct.&amp;nbsp;&lt;/P&gt;
&lt;P&gt;I am trying to collect PCIE_DATA_BYTES derived event from page 34 &amp;nbsp;of "xeon e5 2600 uncore guide". The table says that result is a sum of two monitored events counters, one is TOR_INSERTS.OPCODE opc=0x194 and another TOR_INSERTS.OPCODE opc=0x19C.&amp;nbsp;&lt;/P&gt;
&lt;P&gt;As I understood from guide for each CBo I can collect only one filtered event a time. So it means in this case I have two options to collect required date for specific time range.&lt;/P&gt;
&lt;P&gt;Assuming that workload is uniform on time and in sense of memory addresses accesses.&lt;/P&gt;
&lt;P&gt;1. Split all CBo on two groups and collect events with one opc for one and with another opc for second, and then just extrapolate result or simply multiply by four.&lt;/P&gt;
&lt;P&gt;2. Split monitoring time on two halves and first monitor event with one opc and then with another. Results are simply added.&lt;/P&gt;
&lt;P&gt;The choice of option depends from type of workload.&lt;/P&gt;
&lt;P&gt;Do I miss any other options?&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Thanks for any thoughts.&lt;/P&gt;
&lt;P&gt;Alexander&lt;/P&gt;
&lt;P&gt;&lt;/P&gt;
&lt;P&gt;&lt;/P&gt;
&lt;P&gt;&lt;/P&gt;</description>
      <pubDate>Thu, 30 May 2013 09:24:57 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Tuning-Performance/Collect-TOR-INSERTS-OPCODE-for-two-opcodes-simultaneously/m-p/975305#M2923</guid>
      <dc:creator>Alexander_Alexeev</dc:creator>
      <dc:date>2013-05-30T09:24:57Z</dc:date>
    </item>
    <item>
      <title>Hello Alexander,</title>
      <link>https://community.intel.com/t5/Software-Tuning-Performance/Collect-TOR-INSERTS-OPCODE-for-two-opcodes-simultaneously/m-p/975306#M2924</link>
      <description>&lt;P&gt;Hello Alexander,&lt;/P&gt;
&lt;P&gt;I think you've got it right. Note that the&amp;nbsp;opcodes&amp;nbsp;0x194 and 0x19c look like just PCIe writes into the LLC (if I understand correctly).&amp;nbsp; It looks like the size in bytes for the 0x194 opcode is assumed to be 1 byte. That sounds like a swag to me. Usually when I see&amp;nbsp;events like this I think: one event is showing a full cache line transfer and another showing a "not sure what the size is but, it is probably&amp;nbsp;not cached, and&amp;nbsp;it is less than 64 bytes, might be 1, 2, 4, 8 or 16 bytes". Hopefully the the 0x194 counts are small so the fuzziness doesn't mess you up.&lt;/P&gt;
&lt;P&gt;Pat&lt;/P&gt;</description>
      <pubDate>Thu, 30 May 2013 13:57:34 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Tuning-Performance/Collect-TOR-INSERTS-OPCODE-for-two-opcodes-simultaneously/m-p/975306#M2924</guid>
      <dc:creator>Patrick_F_Intel1</dc:creator>
      <dc:date>2013-05-30T13:57:34Z</dc:date>
    </item>
    <item>
      <title>Alexander,</title>
      <link>https://community.intel.com/t5/Software-Tuning-Performance/Collect-TOR-INSERTS-OPCODE-for-two-opcodes-simultaneously/m-p/975307#M2925</link>
      <description>&lt;P&gt;Alexander,&lt;/P&gt;
&lt;P&gt;you might be interested in the new pcm-pcie utility in Intel(r) PCM 2.5:&amp;nbsp;&lt;A href="http://software.intel.com/en-us/forums/topic/393529"&gt;http://software.intel.com/en-us/forums/topic/393529&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;--&lt;/P&gt;
&lt;P&gt;Roman&lt;/P&gt;</description>
      <pubDate>Fri, 07 Jun 2013 08:14:38 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Tuning-Performance/Collect-TOR-INSERTS-OPCODE-for-two-opcodes-simultaneously/m-p/975307#M2925</guid>
      <dc:creator>Roman_D_Intel</dc:creator>
      <dc:date>2013-06-07T08:14:38Z</dc:date>
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