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    <title>topic Thanks! in Software Tuning, Performance Optimization &amp; Platform Monitoring</title>
    <link>https://community.intel.com/t5/Software-Tuning-Performance/MEM-LOAD-UOPS-MISC-RETIRED-LLC-MISS-PS-opcode-for-sandy-bridge/m-p/978684#M3022</link>
    <description>&lt;P&gt;Thanks!&lt;/P&gt;
&lt;P&gt;Is "special" here "PEBS" ? Can I ignore programming the PEBS bits if I don't care about the events themselves and just want counter / sample triggers?&lt;/P&gt;
&lt;P&gt;Thanks!&lt;/P&gt;
&lt;P&gt;-adrian&lt;/P&gt;</description>
    <pubDate>Sun, 25 Aug 2013 11:52:49 GMT</pubDate>
    <dc:creator>Adrian_C_1</dc:creator>
    <dc:date>2013-08-25T11:52:49Z</dc:date>
    <item>
      <title>MEM_LOAD_UOPS_MISC_RETIRED.LLC_MISS_PS opcode for sandy bridge?</title>
      <link>https://community.intel.com/t5/Software-Tuning-Performance/MEM-LOAD-UOPS-MISC-RETIRED-LLC-MISS-PS-opcode-for-sandy-bridge/m-p/978676#M3014</link>
      <description>&lt;P&gt;Hi!&lt;/P&gt;
&lt;P&gt;I'm working on the FreeBSD hwpmc support for Sandy Bridge. A lot of the tuning whitepapers and forum posts for Sandy Bridge mention MEM_LOAD_UOPS_MISC_RETIRED.LLC_MISS_PS but I can't find it in the SDM. What's the PMC MSR event ID and unit mask for this event?&lt;/P&gt;
&lt;P&gt;Thanks!&lt;/P&gt;
&lt;P&gt;-adrian&lt;/P&gt;</description>
      <pubDate>Mon, 19 Aug 2013 15:44:38 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Tuning-Performance/MEM-LOAD-UOPS-MISC-RETIRED-LLC-MISS-PS-opcode-for-sandy-bridge/m-p/978676#M3014</guid>
      <dc:creator>Adrian_C_1</dc:creator>
      <dc:date>2013-08-19T15:44:38Z</dc:date>
    </item>
    <item>
      <title>Hello Adrian,</title>
      <link>https://community.intel.com/t5/Software-Tuning-Performance/MEM-LOAD-UOPS-MISC-RETIRED-LLC-MISS-PS-opcode-for-sandy-bridge/m-p/978677#M3015</link>
      <description>&lt;P&gt;Hello Adrian,&lt;/P&gt;
&lt;P&gt;From &lt;A href="https://github.com/andikleen/pmu-tools/blob/master/snb-client.csv"&gt;https://github.com/andikleen/pmu-tools/blob/master/snb-client.csv&lt;/A&gt; it looks like the event code is 0xd4 and umask 0x02.&lt;/P&gt;
&lt;P&gt;Pat&lt;/P&gt;</description>
      <pubDate>Tue, 20 Aug 2013 15:06:14 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Tuning-Performance/MEM-LOAD-UOPS-MISC-RETIRED-LLC-MISS-PS-opcode-for-sandy-bridge/m-p/978677#M3015</guid>
      <dc:creator>Patrick_F_Intel1</dc:creator>
      <dc:date>2013-08-20T15:06:14Z</dc:date>
    </item>
    <item>
      <title>Hi!</title>
      <link>https://community.intel.com/t5/Software-Tuning-Performance/MEM-LOAD-UOPS-MISC-RETIRED-LLC-MISS-PS-opcode-for-sandy-bridge/m-p/978678#M3016</link>
      <description>&lt;P&gt;Hi!&lt;/P&gt;
&lt;P&gt;&lt;/P&gt;
&lt;P&gt;Ok, thanks!&lt;/P&gt;
&lt;P&gt;Next from that guide is this -&amp;nbsp;MEM_LOAD_RETIRED.L3_HIT_PS. The entire formula is:&lt;/P&gt;
&lt;P&gt;&lt;/P&gt;
&lt;P&gt;% of cycles spent on last level cache access (2nd level misses that hit in LLC):&lt;BR /&gt;((MEM_LOAD_RETIRED.L3_HIT_PS * 26) + (MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT_PS &lt;BR /&gt;* 43) +&lt;BR /&gt;(MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM_PS * 60)) / CPU_CLK_UNHALTED.THREAD&lt;/P&gt;
&lt;P&gt;&lt;/P&gt;
&lt;P&gt;(The slide set is: &lt;A href="https://software.intel.com/sites/landingpage/legacy/pdfs/Using_Intel_VTune_Amplifier_XE_on_2nd_Gen_Intel_Core_Family.pdf)" target="_blank"&gt;https://software.intel.com/sites/landingpage/legacy/pdfs/Using_Intel_VTune_Amplifier_XE_on_2nd_Gen_Intel_Core_Family.pdf)&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;&lt;/P&gt;
&lt;P&gt;Thanks!&lt;/P&gt;
&lt;P&gt;&lt;/P&gt;
&lt;P&gt;-adrian&lt;/P&gt;</description>
      <pubDate>Sat, 24 Aug 2013 16:40:13 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Tuning-Performance/MEM-LOAD-UOPS-MISC-RETIRED-LLC-MISS-PS-opcode-for-sandy-bridge/m-p/978678#M3016</guid>
      <dc:creator>Adrian_C_1</dc:creator>
      <dc:date>2013-08-24T16:40:13Z</dc:date>
    </item>
    <item>
      <title>Is there a question?
Pat</title>
      <link>https://community.intel.com/t5/Software-Tuning-Performance/MEM-LOAD-UOPS-MISC-RETIRED-LLC-MISS-PS-opcode-for-sandy-bridge/m-p/978679#M3017</link>
      <description>&lt;P&gt;Is there a question?&lt;/P&gt;
&lt;P&gt;Pat&lt;/P&gt;</description>
      <pubDate>Sat, 24 Aug 2013 17:06:44 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Tuning-Performance/MEM-LOAD-UOPS-MISC-RETIRED-LLC-MISS-PS-opcode-for-sandy-bridge/m-p/978679#M3017</guid>
      <dc:creator>Patrick_F_Intel1</dc:creator>
      <dc:date>2013-08-24T17:06:44Z</dc:date>
    </item>
    <item>
      <title>Ah, yes. I can't seem to find</title>
      <link>https://community.intel.com/t5/Software-Tuning-Performance/MEM-LOAD-UOPS-MISC-RETIRED-LLC-MISS-PS-opcode-for-sandy-bridge/m-p/978680#M3018</link>
      <description>&lt;P&gt;Ah, yes. I can't seem to find the opcode/mask for&amp;nbsp;MEM_LOAD_RETIRED.L3_HIT_PS . Would you be able to help me figure out what that actually refers to?&lt;/P&gt;
&lt;P&gt;Thanks!&lt;/P&gt;
&lt;P&gt;&lt;/P&gt;
&lt;P&gt;-adrian&lt;/P&gt;</description>
      <pubDate>Sat, 24 Aug 2013 17:12:26 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Tuning-Performance/MEM-LOAD-UOPS-MISC-RETIRED-LLC-MISS-PS-opcode-for-sandy-bridge/m-p/978680#M3018</guid>
      <dc:creator>Adrian_C_1</dc:creator>
      <dc:date>2013-08-24T17:12:26Z</dc:date>
    </item>
    <item>
      <title>Yeah... sorry... I figured</title>
      <link>https://community.intel.com/t5/Software-Tuning-Performance/MEM-LOAD-UOPS-MISC-RETIRED-LLC-MISS-PS-opcode-for-sandy-bridge/m-p/978681#M3019</link>
      <description>&lt;P&gt;Yeah... sorry... I figured that out right after I sent my reply. It is the same opcode/mask as the event without _PS. The _PS means it is a precise event so you need to do the programming for precise events.&lt;/P&gt;
&lt;P&gt;Pat&lt;/P&gt;</description>
      <pubDate>Sat, 24 Aug 2013 17:20:08 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Tuning-Performance/MEM-LOAD-UOPS-MISC-RETIRED-LLC-MISS-PS-opcode-for-sandy-bridge/m-p/978681#M3019</guid>
      <dc:creator>Patrick_F_Intel1</dc:creator>
      <dc:date>2013-08-24T17:20:08Z</dc:date>
    </item>
    <item>
      <title>Hm, so D1/04 ?

-adrian</title>
      <link>https://community.intel.com/t5/Software-Tuning-Performance/MEM-LOAD-UOPS-MISC-RETIRED-LLC-MISS-PS-opcode-for-sandy-bridge/m-p/978682#M3020</link>
      <description>&lt;P&gt;Hm, so D1/04 ?&lt;/P&gt;
&lt;P&gt;&lt;/P&gt;
&lt;P&gt;&lt;/P&gt;
&lt;P&gt;-adrian&lt;/P&gt;
&lt;P&gt;&lt;/P&gt;</description>
      <pubDate>Sat, 24 Aug 2013 17:30:56 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Tuning-Performance/MEM-LOAD-UOPS-MISC-RETIRED-LLC-MISS-PS-opcode-for-sandy-bridge/m-p/978682#M3020</guid>
      <dc:creator>Adrian_C_1</dc:creator>
      <dc:date>2013-08-24T17:30:56Z</dc:date>
    </item>
    <item>
      <title>Yes... probably 0xd1/0x04 as</title>
      <link>https://community.intel.com/t5/Software-Tuning-Performance/MEM-LOAD-UOPS-MISC-RETIRED-LLC-MISS-PS-opcode-for-sandy-bridge/m-p/978683#M3021</link>
      <description>&lt;P&gt;Yes... probably 0xd1/0x04 as you suggest. It also might be D2/01. I will have to ask the person who tries to keep track of event renaming and get back to you.&lt;/P&gt;
&lt;P&gt;Pat&lt;/P&gt;</description>
      <pubDate>Sat, 24 Aug 2013 17:48:54 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Tuning-Performance/MEM-LOAD-UOPS-MISC-RETIRED-LLC-MISS-PS-opcode-for-sandy-bridge/m-p/978683#M3021</guid>
      <dc:creator>Patrick_F_Intel1</dc:creator>
      <dc:date>2013-08-24T17:48:54Z</dc:date>
    </item>
    <item>
      <title>Thanks!</title>
      <link>https://community.intel.com/t5/Software-Tuning-Performance/MEM-LOAD-UOPS-MISC-RETIRED-LLC-MISS-PS-opcode-for-sandy-bridge/m-p/978684#M3022</link>
      <description>&lt;P&gt;Thanks!&lt;/P&gt;
&lt;P&gt;Is "special" here "PEBS" ? Can I ignore programming the PEBS bits if I don't care about the events themselves and just want counter / sample triggers?&lt;/P&gt;
&lt;P&gt;Thanks!&lt;/P&gt;
&lt;P&gt;-adrian&lt;/P&gt;</description>
      <pubDate>Sun, 25 Aug 2013 11:52:49 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Tuning-Performance/MEM-LOAD-UOPS-MISC-RETIRED-LLC-MISS-PS-opcode-for-sandy-bridge/m-p/978684#M3022</guid>
      <dc:creator>Adrian_C_1</dc:creator>
      <dc:date>2013-08-25T11:52:49Z</dc:date>
    </item>
    <item>
      <title>Hello Adrian,</title>
      <link>https://community.intel.com/t5/Software-Tuning-Performance/MEM-LOAD-UOPS-MISC-RETIRED-LLC-MISS-PS-opcode-for-sandy-bridge/m-p/978685#M3023</link>
      <description>&lt;P&gt;Hello Adrian,&lt;/P&gt;
&lt;P&gt;Yes you can ignore (not program) the PEBS stuff if you don't want it and just use the event as if it is a not-PEBS event.&lt;/P&gt;
&lt;P&gt;Pat&lt;/P&gt;</description>
      <pubDate>Sun, 25 Aug 2013 13:44:36 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Tuning-Performance/MEM-LOAD-UOPS-MISC-RETIRED-LLC-MISS-PS-opcode-for-sandy-bridge/m-p/978685#M3023</guid>
      <dc:creator>Patrick_F_Intel1</dc:creator>
      <dc:date>2013-08-25T13:44:36Z</dc:date>
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