topic Thanks. Are thse questions to in Software Tuning, Performance Optimization & Platform Monitoring

Sandy Bridge Target Address Decoder (TAD Entries)

sarkar__saptarshi — Mon, 02 Sep 2013 13:29:53 GMT

Hi,

My system has got two sockets with Sandy Bridge Processors. Total RAM is 64 GB and has got NUMA enabled.

I am studying two PCI Registers namely, DRAM Rule Register ( for determining interleaving at socket level); and a TAD Register.

for understanding the address mapping scheme in MC.

My question is although there is no interleaving across sockets/numa nodes i.e each NUMA node

has got 32GB( contiguous with no interleaving as per the DRAM Rule Registers). But still each numa node

has got two TAD entries. Documents say that TAD entries correspond to SAD interleaving schemes. Can anyone

help me explain the existence of such TAD entries in this case even though there''s no SAD interleaving. Is it possible ?

Thanks

Hello Saptarshi,

Patrick_F_Intel1 — Mon, 02 Sep 2013 13:44:55 GMT

Hello Saptarshi,

Which manual (and section) are you referencing? A URL would be helpful. This saves everyone time having to find the info you are referencing.

Thanks

Pat

Hi Patrick,

sarkar__saptarshi — Mon, 02 Sep 2013 14:13:03 GMT

Hi Patrick,

Please see section 4.2.4.6 for detaills regarding DRAM RULE and Section 4.3.2.2 for TAD Register Description in the below document

https://www-ssl.intel.com/content/www/us/en/processors/core/core-i7-lga-2011-datasheet-vol-2.html

And an explanation about the TAD Register is given in the following document and Section No 6.2.1

Intel® Xeon® Processor 7500 Series Datasheet, Volume 2

Thanks

Thanks. Are thse questions to

Patrick_F_Intel1 — Mon, 02 Sep 2013 14:40:11 GMT

Thanks. Are thse questions to solve a problem? If so, can you tell us the problem? Or are they just curiosity or a school project? This will help us prioritize the questions versus work we are expected to be doing.
Pat

Hi Patrick,

sarkar__saptarshi — Mon, 02 Sep 2013 15:01:00 GMT

Hi Patrick,

Its a university research project targetted at achieving considerable power savings on intel based servers based on introducing architecture specific memory management techniques in the linux kernel.

For this it is essential to unravell the memory addressing scheme based on documented information available.

Currently all readings of all required registers related to the MC are done (A few values I have posted in my previous post ).

Now I am trying to make a sense of the values of those registers. For which I require help of the community.

I have attached a text file tabulating a few of those register values for reference.

Thanks