https://community.intel.com/t5/Software-Tuning-Performance/How-to-invalidate-cache-with-EPT-after-modifying-memory/m-p/994677#M3455 <P>I'm trying to narrow down some odd behavior.&nbsp; I configured our hypervisor to catch 0xb faults for disabled interrupts. Then enable the interrupt, but mark the EPT page the IDT vector points at as unreadable.&nbsp; I resume execution which clears the interrupt stack and then throws an ept violation. I then flip the state disabling the interrupt i'm trying and finally&nbsp;re-enable the ept page of the vector and resume execution.&nbsp;&nbsp; Everything works well in bochs.</P> <P>However, when I go to test on our Nehalem processor it loops through the hypervisor randomly&nbsp;multiple times, successfully!&nbsp;Sometimes it&nbsp;loops through just once, as it should, other times it runs the code 10-12 times.&nbsp;&nbsp;Unfortunately each loop through increments a counter skewing our results.&nbsp; It appears as if the instruction&nbsp;has been cached in some way and doesn't use the current version in memory until an update several&nbsp;into the cache. &nbsp;I am wondering&nbsp;if I have mis-configured the cache and it's running off an old version of memory. I've tried to issue and WBINVD, CPUID, read CR3, and disabled caching of the EPT pages and structures.&nbsp;&nbsp;&nbsp; Have i missed something?</P> <P>To put the question specifically: what operations do I have to do to invalidate cached mappings (that I might have missed above) to clear the cache when the hypervisor modifies a&nbsp;guest's memory via its ept pages?</P> <P>&nbsp;</P> <P>&nbsp;</P> Wed, 26 Sep 2012 15:15:19 GMT steven765 2012-09-26T15:15:19Z https://community.intel.com/t5/Software-Tuning-Performance/How-to-invalidate-cache-with-EPT-after-modifying-memory/m-p/994677#M3455 <P>I'm trying to narrow down some odd behavior.&nbsp; I configured our hypervisor to catch 0xb faults for disabled interrupts. Then enable the interrupt, but mark the EPT page the IDT vector points at as unreadable.&nbsp; I resume execution which clears the interrupt stack and then throws an ept violation. I then flip the state disabling the interrupt i'm trying and finally&nbsp;re-enable the ept page of the vector and resume execution.&nbsp;&nbsp; Everything works well in bochs.</P> <P>However, when I go to test on our Nehalem processor it loops through the hypervisor randomly&nbsp;multiple times, successfully!&nbsp;Sometimes it&nbsp;loops through just once, as it should, other times it runs the code 10-12 times.&nbsp;&nbsp;Unfortunately each loop through increments a counter skewing our results.&nbsp; It appears as if the instruction&nbsp;has been cached in some way and doesn't use the current version in memory until an update several&nbsp;into the cache. &nbsp;I am wondering&nbsp;if I have mis-configured the cache and it's running off an old version of memory. I've tried to issue and WBINVD, CPUID, read CR3, and disabled caching of the EPT pages and structures.&nbsp;&nbsp;&nbsp; Have i missed something?</P> <P>To put the question specifically: what operations do I have to do to invalidate cached mappings (that I might have missed above) to clear the cache when the hypervisor modifies a&nbsp;guest's memory via its ept pages?</P> <P>&nbsp;</P> <P>&nbsp;</P> Wed, 26 Sep 2012 15:15:19 GMT https://community.intel.com/t5/Software-Tuning-Performance/How-to-invalidate-cache-with-EPT-after-modifying-memory/m-p/994677#M3455 steven765 2012-09-26T15:15:19Z