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    <title>topic Do you not believe what is in Software Tuning, Performance Optimization &amp; Platform Monitoring</title>
    <link>https://community.intel.com/t5/Software-Tuning-Performance/Is-L2-Cache-Inclusive-to-L1-Instruction-Cache-micro-op-cache-in/m-p/1012191#M3790</link>
    <description>&lt;P&gt;Do you not believe what is written in the architecture docs, not to mention many interesting web pages since Nehalem?&lt;/P&gt;

&lt;P&gt;If you have an assignment to look these things up, why are you asking here for answers which you probably need to check anyway?&lt;/P&gt;

&lt;P&gt;Where it says loop stream detector keeps decoded micro-ops in Instruction Decoder Queue it seems to imply that the instructions cached in L1I or L2 (with exclusivity) remain coded; besides, the stated limits on size of micro-op queue are far smaller than L1.&amp;nbsp; It's a lot like the advertisements, "up to" such and such.&lt;/P&gt;</description>
    <pubDate>Sat, 10 Oct 2015 14:00:59 GMT</pubDate>
    <dc:creator>TimP</dc:creator>
    <dc:date>2015-10-10T14:00:59Z</dc:date>
    <item>
      <title>Is L2 Cache Inclusive to L1 Instruction Cache (micro-op cache) in Intel Sandy Bridge?</title>
      <link>https://community.intel.com/t5/Software-Tuning-Performance/Is-L2-Cache-Inclusive-to-L1-Instruction-Cache-micro-op-cache-in/m-p/1012190#M3789</link>
      <description>&lt;P&gt;Is the micro op cache inclusive to L1 Instruction Cache?&lt;/P&gt;

&lt;P&gt;Is the L2 Cache Inclusive to L1 Instruction Cache?&lt;/P&gt;</description>
      <pubDate>Sat, 10 Oct 2015 00:16:43 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Tuning-Performance/Is-L2-Cache-Inclusive-to-L1-Instruction-Cache-micro-op-cache-in/m-p/1012190#M3789</guid>
      <dc:creator>Steven_P_1</dc:creator>
      <dc:date>2015-10-10T00:16:43Z</dc:date>
    </item>
    <item>
      <title>Do you not believe what is</title>
      <link>https://community.intel.com/t5/Software-Tuning-Performance/Is-L2-Cache-Inclusive-to-L1-Instruction-Cache-micro-op-cache-in/m-p/1012191#M3790</link>
      <description>&lt;P&gt;Do you not believe what is written in the architecture docs, not to mention many interesting web pages since Nehalem?&lt;/P&gt;

&lt;P&gt;If you have an assignment to look these things up, why are you asking here for answers which you probably need to check anyway?&lt;/P&gt;

&lt;P&gt;Where it says loop stream detector keeps decoded micro-ops in Instruction Decoder Queue it seems to imply that the instructions cached in L1I or L2 (with exclusivity) remain coded; besides, the stated limits on size of micro-op queue are far smaller than L1.&amp;nbsp; It's a lot like the advertisements, "up to" such and such.&lt;/P&gt;</description>
      <pubDate>Sat, 10 Oct 2015 14:00:59 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Tuning-Performance/Is-L2-Cache-Inclusive-to-L1-Instruction-Cache-micro-op-cache-in/m-p/1012191#M3790</guid>
      <dc:creator>TimP</dc:creator>
      <dc:date>2015-10-10T14:00:59Z</dc:date>
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