topic Branch Trace Store on x64 Windows in Software Tuning, Performance Optimization & Platform Monitoring

Branch Trace Store on x64 Windows

Marcus_B_ — Tue, 15 Sep 2015 17:33:24 GMT

I'm implementing BTS on x64 W7 and W8 as part of my academic research and I got a problem: I've set up everything (as far as I know) but I can't get being interrupted on BTS overflow. I have set up DS AREA and I can manually inspect the memory and check everything is fine ( BTS recorded until threshold). However, no interrupt is generated. I checked: APIC is set to edge and fixed, and its vector value is 254. I read IDTR and set IDT[254] to point my interrupt routine. BTINT is set on DEBUGCTL. Did I forget something ? Could anyone of you experienced with Windows implementation help me ? Besides, Are there any implementation piece available ? I found some on Linux, but none on Windows. Thanks in advance, Marcus

Edit: I left a question on Microsoft's Forums but they aren't sure about Intel's things.

Well, since I asked such

Marcus_B_ — Sat, 26 Sep 2015 17:38:21 GMT

Well, since I asked such question I did a great effort on developing my implementation. Currently I developed a new device driver and handled PnP issues for registering a interrupt. However, I am still not sure about how to perform such registration. APIC LVT [254] is a windows used IRQ. I really don't know if I should pretend to have a message interrupt or any other approach. I'm sure you can help me since Intel Vtune makes use of such BTS capabilites on Windows. If I asked on a wrong forum section, please move to an appropriated one. Thanks in advance, Marcus

My current doubt is how to

Marcus_B_ — Tue, 29 Sep 2015 16:59:06 GMT

My current doubt is how to register the correct IRQ. I can't set up 254 IRQ once it is already in use by the system. I can register another number, however I don't know how to redirect it. Any Ideia ?

perhaps you can find similar

SHIH_K_Intel — Tue, 29 Sep 2015 22:01:03 GMT

perhaps you can find similar situations in some open source porject to learn/practice the necessary programming mechanics dealing with setting up overflow interrupt caused by an buffer overflow condition. A proling tool project supporting sample-after mode of performance counter data gathering could provide the detail mechanics: buffer overflow -> counter overflow, BTINT in debugctl -> INT in the perfevtsel, etc..

I checked linux

Marcus_B_ — Thu, 08 Oct 2015 21:59:22 GMT

I checked linux implementation. I was able to handle interruptions both by using request_irq on a shared APIC entry, either by using NMI interruptions. However, I need that on Windows environment. I tried to register a shared IRQ but windows returns error 12 "This device cannot find enough free resources" I tried to change APIC to NMI and register a NMI callback, but nothing happens. Any ideias ?

I finally registered my ISR

Marcus_B_ — Tue, 13 Oct 2015 16:22:32 GMT

I finally registered my ISR routine, but I am not being interrupted. I am looking to see if my configuration is correct. I set DS MSR with the BTS structure, and I checked: addresses are correctly written. I set DEBUGCTL MSR with BTS, BTINT and LBR flags. Is is enough to generate the interruption ? Should I set something more, like MSR_PERF_GLOBAL MSR or other ? Thanks, Marcus