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    <title>topic Back-End/Front-End Stall is a in Software Tuning, Performance Optimization &amp; Platform Monitoring</title>
    <link>https://community.intel.com/t5/Software-Tuning-Performance/Unfilled-slots-back-end-front-end-bound/m-p/1029697#M4244</link>
    <description>&lt;P&gt;Back-End/Front-End Stall is a measure of the delay or stall in code stream execution by the CPU processing pipeline. For example good description of Front-End stall can be synchronous wait of the CPU for memory access (assume cache misses) in such a situation execution stack must wait for completion of memory transfers in order to continue execution. Situation can get worse in the term of CPI when the code is highly interdependent so in this case CPU cannot easily perform OOE here of course there is a clear dependency on the amount of prefetched instructions and size of corresponding uops buffers.&lt;/P&gt;</description>
    <pubDate>Sun, 24 Aug 2014 17:04:08 GMT</pubDate>
    <dc:creator>Bernard</dc:creator>
    <dc:date>2014-08-24T17:04:08Z</dc:date>
    <item>
      <title>Unfilled slots back end / front end bound</title>
      <link>https://community.intel.com/t5/Software-Tuning-Performance/Unfilled-slots-back-end-front-end-bound/m-p/1029695#M4242</link>
      <description>&lt;P&gt;Can someone clarify for me what the backend / frontend bound figures represent in the general exploration section of VTune Amplifier XE, I suspect they are calculated using some function of clock cycles / ( slots or instructions ), could someone please provide the exact formula for this, secondly is there any threshold beyond which these figures are deemed to be bad, for example a CPI of 1 is deemed to by not good, is there anything similar that applies to the front end and back end bound figures, finally is there a way of relating the front end bound and back end bound figures to CPI ?&lt;/P&gt;</description>
      <pubDate>Sun, 24 Aug 2014 15:42:23 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Tuning-Performance/Unfilled-slots-back-end-front-end-bound/m-p/1029695#M4242</guid>
      <dc:creator>Chris_A_</dc:creator>
      <dc:date>2014-08-24T15:42:23Z</dc:date>
    </item>
    <item>
      <title>Here are some references for</title>
      <link>https://community.intel.com/t5/Software-Tuning-Performance/Unfilled-slots-back-end-front-end-bound/m-p/1029696#M4243</link>
      <description>&lt;P&gt;Here are some references for the front-end/back-end analsysis, called the topdown analysis by some Intel folks.&lt;/P&gt;

&lt;P&gt;From &lt;A href="http://halobates.de/blog/p/category/monitoring"&gt;http://halobates.de/blog/p/category/monitoring&lt;/A&gt; :&lt;/P&gt;

&lt;P&gt;&lt;IMG width="960" height="100" alt="" src="http://halobates.de/ivb-hierarchy.svg" /&gt;&lt;/P&gt;

&lt;P&gt;From &lt;A href="https://sites.google.com/site/analysismethods/isca2013/program-1"&gt;https://sites.google.com/site/analysismethods/isca2013/program-1&lt;/A&gt; there is a topdown presentation:&lt;/P&gt;

&lt;P&gt;&lt;A href="https://docs.google.com/viewer?a=v&amp;amp;pid=sites&amp;amp;srcid=ZGVmYXVsdGRvbWFpbnxhbmFseXNpc21ldGhvZHN8Z3g6MWJjNTE2OTU4ODVlZGFkMw"&gt;https://docs.google.com/viewer?a=v&amp;amp;pid=sites&amp;amp;srcid=ZGVmYXVsdGRvbWFpbnxhbmFseXNpc21ldGhvZHN8Z3g6MWJjNTE2OTU4ODVlZGFkMw&lt;/A&gt;&lt;/P&gt;

&lt;P&gt;Hopefully this will make things clearer.&lt;/P&gt;

&lt;P&gt;Pat&lt;/P&gt;</description>
      <pubDate>Sun, 24 Aug 2014 16:43:33 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Tuning-Performance/Unfilled-slots-back-end-front-end-bound/m-p/1029696#M4243</guid>
      <dc:creator>Patrick_F_Intel1</dc:creator>
      <dc:date>2014-08-24T16:43:33Z</dc:date>
    </item>
    <item>
      <title>Back-End/Front-End Stall is a</title>
      <link>https://community.intel.com/t5/Software-Tuning-Performance/Unfilled-slots-back-end-front-end-bound/m-p/1029697#M4244</link>
      <description>&lt;P&gt;Back-End/Front-End Stall is a measure of the delay or stall in code stream execution by the CPU processing pipeline. For example good description of Front-End stall can be synchronous wait of the CPU for memory access (assume cache misses) in such a situation execution stack must wait for completion of memory transfers in order to continue execution. Situation can get worse in the term of CPI when the code is highly interdependent so in this case CPU cannot easily perform OOE here of course there is a clear dependency on the amount of prefetched instructions and size of corresponding uops buffers.&lt;/P&gt;</description>
      <pubDate>Sun, 24 Aug 2014 17:04:08 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Tuning-Performance/Unfilled-slots-back-end-front-end-bound/m-p/1029697#M4244</guid>
      <dc:creator>Bernard</dc:creator>
      <dc:date>2014-08-24T17:04:08Z</dc:date>
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