topic Is there a difference between in Software Tuning, Performance Optimization & Platform Monitoring

Intel PCM- Unsupported Processor Model error (Intel(R) Xeon(R) CPU E7-4860 v2 @ 2.60GHz (62))

Mahwish_A_ — Mon, 15 Jun 2015 15:04:30 GMT

I am running PCM (version 2.8) numa and power utilities on Ivy Bridge platform (Intel(R) Xeon(R) CPU E7-4860 v2) Model 62 but getting this "Unsupported Processor Model" error. pcm-power reads returns my model number as -1. Is it not supported by PCM v2.8?

Could you please post the

Roman_D_Intel — Mon, 15 Jun 2015 16:13:11 GMT

Could you please post the entire output of pcm-power and pcm-numa?

Thank you,

Roman

Mahwish_A_ — Tue, 16 Jun 2015 11:09:14 GMT

Roman

I get the following message for pcm-numa and pca-power respectively:

"pcm-numa tool does not support your processor currently."

"Unsupported processor model (-1)"

I think the problem was

Mahwish_A_ — Tue, 16 Jun 2015 13:02:26 GMT

I think the problem was because of NMI watchdog which was enabled. After disabling it, PCM now detects the model.

Thanks for you message. We

Roman_D_Intel — Fri, 19 Jun 2015 12:15:46 GMT

Thanks for you message. We will improve the error reporting in the next version of the code.

As mentioned above, I am

Mahwish_A_ — Fri, 19 Jun 2015 12:39:40 GMT

As mentioned above, I am running pcm-numa.x on Ivy Bridge platform model 62 (Xeon E7 v2). PCM can detect my model number 62 but classifies it as IVYTOWN instead of IVY_BRIDGE due to the definition in enum SupportedCPUModels . I swapped the definition of IVY_BRIDGE and IVYTOWN in SupportedCPUModels (IVY_BRIDGE=62, IVYTOWN =58) so that it that correctly identifies the architecture too.

Now when pcm-numa.x calls initUncoreObjects() function, I get the following error:

"Can not read memory controller counter information from PCI configuration space. Access to memory bandwidth counters is not possible.You must be root to access these SandyBridge/IvyBridge/Haswell counters in PCM."

I am not running pcm-numa.x with root access but I do have R/W access to MSR registers. Can you advise on this?

1) You should not change the

Roman_D_Intel — Fri, 19 Jun 2015 12:44:06 GMT

1) You should not change the CPU ID. The server processor (E7/E5 v2) with the Ivybridge uarchitecture had the codename IVYTOWN.

2) You need root access to access uncore memory counters.

for 2) PCM accesses the root

Roman_D_Intel — Fri, 19 Jun 2015 12:45:46 GMT

for 2) PCM accesses the root /dev/mem driver to program uncore PMU. Uncore PMU on Ivytown does not have msr interface.

Is there a difference between

Mahwish_A_ — Sat, 20 Jun 2015 14:42:07 GMT

Is there a difference between offcore and uncore events? As I understand anything that any function which is not on the core is Uncore/Offcore e.g. L3/LLC etc? However, Intel lists OFFCORE_RESPONSE_X and uncore events separately. Is it different to program an uncore event than an offcore? As given in pcm-numa.x, OFFCORE_RESPONSE_X for IvyTown is also programmed using event select registers and MSRs.

The uncore and offcore

Roman_D_Intel — Mon, 22 Jun 2015 10:20:49 GMT

The uncore and offcore response events are counted in different performance monitoring units (PMUs). The offcore response events are programmed in the core PMU.

pcm-numa uses the offcore response events, so the lack of access to the uncore PMUs should not result in an issue.

Best regards,

Roman