https://community.intel.com/t5/Software-Tuning-Performance/LLCM/m-p/1040906#M4565 <P>Hi GHui,</P> <P>longest latency cache miss rate should be&nbsp;<A href="https://software.intel.com/sites/products/documentation/doclib/stdxe/2013SP1/amplifierxe/pmn/events/longest_lat_cache.html">LONGEST_LAT_CACHE.MISS/</A><SPAN style="font-size: 13.0080003738403px; line-height: 19.5120010375977px;"><A href="https://software.intel.com/sites/products/documentation/doclib/stdxe/2013SP1/amplifierxe/pmn/events/longest_lat_cache.html">LONGEST_LAT_CACHE.REFERENCE</A>&nbsp;</SPAN></P> <P><SPAN style="font-size: 13.0080003738403px; line-height: 19.5120010375977px;">Thanks,</SPAN></P> <P><SPAN style="font-size: 13.0080003738403px; line-height: 19.5120010375977px;">Roman</SPAN></P> Mon, 31 Aug 2015 14:45:00 GMT Roman_D_Intel 2015-08-31T14:45:00Z https://community.intel.com/t5/Software-Tuning-Performance/LLCM/m-p/1040905#M4564 <P>I calc llcm. It's about 60%, when I run vasp.</P> <P>I use the following formula</P> <P>LONGEST_LAT_CACHE.MISS * 100&nbsp; /&nbsp; (&nbsp;LONGEST_LAT_CACHE.MISS +&nbsp;MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM +&nbsp;MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT )</P> <P>I've no idea about if this is right.</P> Wed, 05 Aug 2015 10:11:01 GMT https://community.intel.com/t5/Software-Tuning-Performance/LLCM/m-p/1040905#M4564 GHui 2015-08-05T10:11:01Z https://community.intel.com/t5/Software-Tuning-Performance/LLCM/m-p/1040906#M4565 <P>Hi GHui,</P> <P>longest latency cache miss rate should be&nbsp;<A href="https://software.intel.com/sites/products/documentation/doclib/stdxe/2013SP1/amplifierxe/pmn/events/longest_lat_cache.html">LONGEST_LAT_CACHE.MISS/</A><SPAN style="font-size: 13.0080003738403px; line-height: 19.5120010375977px;"><A href="https://software.intel.com/sites/products/documentation/doclib/stdxe/2013SP1/amplifierxe/pmn/events/longest_lat_cache.html">LONGEST_LAT_CACHE.REFERENCE</A>&nbsp;</SPAN></P> <P><SPAN style="font-size: 13.0080003738403px; line-height: 19.5120010375977px;">Thanks,</SPAN></P> <P><SPAN style="font-size: 13.0080003738403px; line-height: 19.5120010375977px;">Roman</SPAN></P> Mon, 31 Aug 2015 14:45:00 GMT https://community.intel.com/t5/Software-Tuning-Performance/LLCM/m-p/1040906#M4565 Roman_D_Intel 2015-08-31T14:45:00Z