<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic On Intel you have MEM_UOPS in Software Tuning, Performance Optimization &amp; Platform Monitoring</title>
    <link>https://community.intel.com/t5/Software-Tuning-Performance/Counting-MFENCE-events-with-performance-counters/m-p/1042353#M4583</link>
    <description>&lt;P&gt;On Intel you have&amp;nbsp;MEM_UOPS_RETIRED.LOCK_LOADS/MEM_UOPS_RETIRED.LOCK_STORES&amp;nbsp; events. However they work best with disabled Hyper-Threading.&lt;/P&gt;

&lt;P&gt;Roman&lt;/P&gt;</description>
    <pubDate>Fri, 31 Oct 2014 15:11:59 GMT</pubDate>
    <dc:creator>Roman_D_Intel</dc:creator>
    <dc:date>2014-10-31T15:11:59Z</dc:date>
    <item>
      <title>Counting MFENCE events with performance counters</title>
      <link>https://community.intel.com/t5/Software-Tuning-Performance/Counting-MFENCE-events-with-performance-counters/m-p/1042352#M4582</link>
      <description>&lt;P&gt;Hi All,&lt;/P&gt;

&lt;P&gt;I'm wondering if there is a performance counter for retired MFENCE instructions or perhaps another counter that could provide something similar. I've googled a bit, and it looks like AMD has such a counter but I've seen nothing for Intel. Ditto on lock prefix instructions...I haven't seen anything for those either.&lt;/P&gt;

&lt;P&gt;Thanks for the help!&lt;/P&gt;

&lt;P&gt;Tim&lt;/P&gt;</description>
      <pubDate>Fri, 31 Oct 2014 13:53:14 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Tuning-Performance/Counting-MFENCE-events-with-performance-counters/m-p/1042352#M4582</guid>
      <dc:creator>Tim_M_1</dc:creator>
      <dc:date>2014-10-31T13:53:14Z</dc:date>
    </item>
    <item>
      <title>On Intel you have MEM_UOPS</title>
      <link>https://community.intel.com/t5/Software-Tuning-Performance/Counting-MFENCE-events-with-performance-counters/m-p/1042353#M4583</link>
      <description>&lt;P&gt;On Intel you have&amp;nbsp;MEM_UOPS_RETIRED.LOCK_LOADS/MEM_UOPS_RETIRED.LOCK_STORES&amp;nbsp; events. However they work best with disabled Hyper-Threading.&lt;/P&gt;

&lt;P&gt;Roman&lt;/P&gt;</description>
      <pubDate>Fri, 31 Oct 2014 15:11:59 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Tuning-Performance/Counting-MFENCE-events-with-performance-counters/m-p/1042353#M4583</guid>
      <dc:creator>Roman_D_Intel</dc:creator>
      <dc:date>2014-10-31T15:11:59Z</dc:date>
    </item>
    <item>
      <title>Thanks Roman, what about for</title>
      <link>https://community.intel.com/t5/Software-Tuning-Performance/Counting-MFENCE-events-with-performance-counters/m-p/1042354#M4584</link>
      <description>&lt;P&gt;Thanks Roman, what about for memory fences?&lt;/P&gt;</description>
      <pubDate>Fri, 31 Oct 2014 16:26:12 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Tuning-Performance/Counting-MFENCE-events-with-performance-counters/m-p/1042354#M4584</guid>
      <dc:creator>Tim_M_1</dc:creator>
      <dc:date>2014-10-31T16:26:12Z</dc:date>
    </item>
    <item>
      <title>I am not aware of FENCE</title>
      <link>https://community.intel.com/t5/Software-Tuning-Performance/Counting-MFENCE-events-with-performance-counters/m-p/1042355#M4585</link>
      <description>&lt;P&gt;I am not aware of FENCE events.&lt;/P&gt;

&lt;P&gt;Roman&lt;/P&gt;</description>
      <pubDate>Wed, 26 Nov 2014 13:12:04 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Tuning-Performance/Counting-MFENCE-events-with-performance-counters/m-p/1042355#M4585</guid>
      <dc:creator>Roman_D_Intel</dc:creator>
      <dc:date>2014-11-26T13:12:04Z</dc:date>
    </item>
  </channel>
</rss>

