Xeon E5/E5v2 performance counters - not all counters working for all events

Jacob_M_ — Tue, 09 Sep 2014 13:06:51 GMT

Hi,

I'm working with a Xeon E5-1650 and a Xeon E5-2697 v2. Each model has 8 performance counters according to CPUID. However, I'm finding that counters 4-7 refuse to log certain events. For example, if I program all counters to log MEM_LOAD_UOPS_RETIRED.L1_HIT then only the first 4 counters increment. If I program all counters to use another event, like CPU_CLK_UNHALTED.THREAD_P, then all 8 counters increment.

I can't find anything in the docs that specifies which counters are capable of logging which events - is this expected behavior?

Many thanks.

Hello Jacob,

Patrick_F_Intel1 — Tue, 09 Sep 2014 16:35:38 GMT

Hello Jacob,

The Ivybridge (IVB) core PMU (Performance monitoring unit) is similar to the Sandybridge (SNB) PMU. See the June 2014 SDM vol 3, section 18.10.

The SNB core PMU supports 8 general counters if CPUID.0AH:EAX[15:8] = 8 and 4 counters if CPUID.0AH:EAX[15:8] = 4. Basically if Hyper-Threading (HT) is enabled then you get 4 counters and 8 counters if HT is disabled. See section 18.9.1 and 18.9.2.

The PEBS events can't be programmed in gen counters 4-7 (PMC4-7). See SDM table 18.46.

Also from section 18.9.4: PEBS events are only valid when the following fields of IA32_PERFEVTSELx are all zero: AnyThread, Edge, Invert, CMask. Also, only PMC3 can be used to capture precise store events. If you setting MEM_LOAD_UOPS_RETIRED.L1_HIT as a precise event then it will not count in PMC4-7.

Hope this helps,

Pat

topic Xeon E5/E5v2 performance counters - not all counters working for all events in Software Tuning, Performance Optimization & Platform Monitoring

Xeon E5/E5v2 performance counters - not all counters working for all events

Hello Jacob,