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    <title>topic Thanks for the clarification. in Software Tuning, Performance Optimization &amp; Platform Monitoring</title>
    <link>https://community.intel.com/t5/Software-Tuning-Performance/Question-on-PCM-function-getCyclesLostDueL3CacheMisses/m-p/1045660#M4679</link>
    <description>&lt;P&gt;Thanks for the clarification. If you're removing the L3clk/L2clk metrics, is there an alternate route to estimate the amount of time the cores spent waiting on an L3 miss (which would mostly be waiting on DDR, assuming good threading)?&lt;/P&gt;

&lt;P&gt;Thanks,&lt;/P&gt;

&lt;P&gt;Pradeep.&lt;/P&gt;</description>
    <pubDate>Mon, 10 Aug 2015 07:09:46 GMT</pubDate>
    <dc:creator>Pradeep_R_</dc:creator>
    <dc:date>2015-08-10T07:09:46Z</dc:date>
    <item>
      <title>Question on PCM function getCyclesLostDueL3CacheMisses()</title>
      <link>https://community.intel.com/t5/Software-Tuning-Performance/Question-on-PCM-function-getCyclesLostDueL3CacheMisses/m-p/1045658#M4677</link>
      <description>&lt;P&gt;Hi, In the function getCyclesLostDueL3CacheMisses() defined in cpucounters.h of the PCM package, I see a 180. * L3_cycles/total_cycles computation as return value. Can someone please explain why there is a 180 there, and no a 100? Thanks, Pradeep.&lt;/P&gt;</description>
      <pubDate>Mon, 10 Aug 2015 05:36:59 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Tuning-Performance/Question-on-PCM-function-getCyclesLostDueL3CacheMisses/m-p/1045658#M4677</guid>
      <dc:creator>Pradeep_R_</dc:creator>
      <dc:date>2015-08-10T05:36:59Z</dc:date>
    </item>
    <item>
      <title>Hi Pradeep,</title>
      <link>https://community.intel.com/t5/Software-Tuning-Performance/Question-on-PCM-function-getCyclesLostDueL3CacheMisses/m-p/1045659#M4678</link>
      <description>&lt;P&gt;Hi Pradeep,&lt;/P&gt;

&lt;P&gt;This was an average memory access latency for a 2-socket system. Since this is only a rough estimation method we have deprecated this function and the L3CLK/L2CLK metrics in the upcoming PCM version.&lt;/P&gt;

&lt;P&gt;Best regards,&lt;/P&gt;

&lt;P&gt;Roman&lt;/P&gt;</description>
      <pubDate>Mon, 10 Aug 2015 06:52:00 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Tuning-Performance/Question-on-PCM-function-getCyclesLostDueL3CacheMisses/m-p/1045659#M4678</guid>
      <dc:creator>Roman_D_Intel</dc:creator>
      <dc:date>2015-08-10T06:52:00Z</dc:date>
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    <item>
      <title>Thanks for the clarification.</title>
      <link>https://community.intel.com/t5/Software-Tuning-Performance/Question-on-PCM-function-getCyclesLostDueL3CacheMisses/m-p/1045660#M4679</link>
      <description>&lt;P&gt;Thanks for the clarification. If you're removing the L3clk/L2clk metrics, is there an alternate route to estimate the amount of time the cores spent waiting on an L3 miss (which would mostly be waiting on DDR, assuming good threading)?&lt;/P&gt;

&lt;P&gt;Thanks,&lt;/P&gt;

&lt;P&gt;Pradeep.&lt;/P&gt;</description>
      <pubDate>Mon, 10 Aug 2015 07:09:46 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Tuning-Performance/Question-on-PCM-function-getCyclesLostDueL3CacheMisses/m-p/1045660#M4679</guid>
      <dc:creator>Pradeep_R_</dc:creator>
      <dc:date>2015-08-10T07:09:46Z</dc:date>
    </item>
    <item>
      <title>Hi Pradeep,</title>
      <link>https://community.intel.com/t5/Software-Tuning-Performance/Question-on-PCM-function-getCyclesLostDueL3CacheMisses/m-p/1045661#M4680</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;SPAN style="font-size: 12px; line-height: 18px;"&gt;Pradeep,&lt;/SPAN&gt;&lt;/P&gt;

&lt;P&gt;&lt;SPAN style="font-size: 12px; line-height: 18px;"&gt;I could recommend the top-down method implemented in the "&lt;A href="https://software.intel.com/en-us/articles/understanding-how-general-exploration-works-in-intel-vtune-amplifier-xe"&gt;General Exploration"&lt;/A&gt; analysis&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN style="color: rgb(102, 102, 102); font-family: Arial, Tahoma, Helvetica, sans-serif; font-size: 14px; line-height: 19.6000003814697px;"&gt;of Intel® VTune™ Amplifier XE. It is a much more robust method to analyze CPU stalls (incl L3 cache miss stalls).&lt;/SPAN&gt;&lt;/P&gt;

&lt;P&gt;&lt;SPAN style="color: rgb(102, 102, 102); font-family: Arial, Tahoma, Helvetica, sans-serif; font-size: 14px; line-height: 19.6000003814697px;"&gt;Best regards,&lt;/SPAN&gt;&lt;/P&gt;

&lt;P&gt;&lt;SPAN style="color: rgb(102, 102, 102); font-family: Arial, Tahoma, Helvetica, sans-serif; font-size: 14px; line-height: 19.6000003814697px;"&gt;Roman&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Mon, 10 Aug 2015 07:15:42 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Tuning-Performance/Question-on-PCM-function-getCyclesLostDueL3CacheMisses/m-p/1045661#M4680</guid>
      <dc:creator>Roman_D_Intel</dc:creator>
      <dc:date>2015-08-10T07:15:42Z</dc:date>
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