<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic So I found that I can control in Software Tuning, Performance Optimization &amp; Platform Monitoring</title>
    <link>https://community.intel.com/t5/Software-Tuning-Performance/Disable-C6-C7-C-state-for-core/m-p/1045854#M4686</link>
    <description>&lt;P&gt;So I found that I can control the c-state individually for each core by just writing '0' or '1' to file&amp;nbsp;/sys/devices/system/cpu/cpu[0123]/cpuidle/state[012345]/disable. I am wondering if there are any downsides to controlling c-states this way!&lt;/P&gt;</description>
    <pubDate>Wed, 24 Jun 2015 17:59:00 GMT</pubDate>
    <dc:creator>BGoel</dc:creator>
    <dc:date>2015-06-24T17:59:00Z</dc:date>
    <item>
      <title>Disable C6/C7 C-state for core</title>
      <link>https://community.intel.com/t5/Software-Tuning-Performance/Disable-C6-C7-C-state-for-core/m-p/1045849#M4681</link>
      <description>&lt;P&gt;Is there a way to prevent the core from going to C6/C7 C-state? I looked into my BIOS and it only provides support for disabling package C-states but not core c-states.&lt;/P&gt;</description>
      <pubDate>Fri, 19 Jun 2015 12:45:46 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Tuning-Performance/Disable-C6-C7-C-state-for-core/m-p/1045849#M4681</guid>
      <dc:creator>BGoel</dc:creator>
      <dc:date>2015-06-19T12:45:46Z</dc:date>
    </item>
    <item>
      <title>In Linux systems the core C</title>
      <link>https://community.intel.com/t5/Software-Tuning-Performance/Disable-C6-C7-C-state-for-core/m-p/1045850#M4682</link>
      <description>&lt;P&gt;In Linux systems the core C-states can be disabled using by modifying a boot time option and then using a bizarre interface.&lt;/P&gt;

&lt;P&gt;First, you need to disable the "intel_idle" C-state governor by adding the boot option "intel_idle.max_cstate=0" and rebooting the system.&lt;/P&gt;

&lt;P&gt;Second, you need to write a program that opens the file "/dev/cpu_dma_latency", writes a 32-bit binary value to the file, and then &lt;STRONG&gt;&lt;EM&gt;keeps the file open&lt;/EM&gt;&lt;/STRONG&gt;.&amp;nbsp;&amp;nbsp; If you close the file, the system reverts to the default behavior (which will allow all C-states).&amp;nbsp; Sample routines for this purpose are provided at &lt;A href="https://access.redhat.com/articles/65410" target="_blank"&gt;https://access.redhat.com/articles/65410&lt;/A&gt;&lt;/P&gt;

&lt;P&gt;The value that you write is the maximum number of microseconds that the OS will allow for a processor to recover from a C-state.&amp;nbsp; For the Xeon E5-2680 (Sandy Bridge) processors in my systems, the recovery times (also in microseconds) can be seen by&lt;/P&gt;

&lt;BLOCKQUOTE&gt;
	&lt;P&gt;$ cat /sys/devices/system/cpu/cpu0/cpuidle/state[01234]/latency&lt;BR /&gt;
		0&lt;BR /&gt;
		1&lt;BR /&gt;
		80&lt;BR /&gt;
		104&lt;BR /&gt;
		109&lt;/P&gt;
&lt;/BLOCKQUOTE&gt;

&lt;P&gt;C0 has a "recovery time" of 0 microseconds, since it is the active state.&amp;nbsp;&amp;nbsp; C1 has a recovery time of ~1 microsecond, but still saves a fair amount of power.&amp;nbsp;&amp;nbsp; We typically use 75 microseconds to prevent C-states with higher numbers than C1.&lt;/P&gt;

&lt;P&gt;Although I don't understand the details, there is not a 1:1 correspondence between the ACPI C-states used by the "cpuidle" facility and the hardware C-states as actually implemented by the processor.&amp;nbsp; You can certainly block all states with numbers higher than C1, but it is not clear whether this interface will allow control at finer granularity.&lt;/P&gt;

&lt;P&gt;&amp;nbsp;&lt;/P&gt;

&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Fri, 19 Jun 2015 15:57:08 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Tuning-Performance/Disable-C6-C7-C-state-for-core/m-p/1045850#M4682</guid>
      <dc:creator>McCalpinJohn</dc:creator>
      <dc:date>2015-06-19T15:57:08Z</dc:date>
    </item>
    <item>
      <title>Thanks John as always. It</title>
      <link>https://community.intel.com/t5/Software-Tuning-Performance/Disable-C6-C7-C-state-for-core/m-p/1045851#M4683</link>
      <description>&lt;P&gt;Thanks John as always. It worked great. But I am not sure I understand why I need to use the boot option "intel_idle.max_cstate=0". When I use this option, I see cpuidle states from state0 to state2 at /sys/devices/system/cpu/cpu0/cpuidle/. But when I don't use this option, state0 to state5 are visible. In both the cases, I am able to control which c-state the processor is allowed to go by writing the appropriate value in cpu_dma_latency file.&lt;/P&gt;</description>
      <pubDate>Tue, 23 Jun 2015 18:45:11 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Tuning-Performance/Disable-C6-C7-C-state-for-core/m-p/1045851#M4683</guid>
      <dc:creator>BGoel</dc:creator>
      <dc:date>2015-06-23T18:45:11Z</dc:date>
    </item>
    <item>
      <title>My understanding is that the</title>
      <link>https://community.intel.com/t5/Software-Tuning-Performance/Disable-C6-C7-C-state-for-core/m-p/1045852#M4684</link>
      <description>&lt;P&gt;My understanding is that the Intel idle driver can ignore BIOS and/or OS requests to not use the higher-numbered C-states.&amp;nbsp; If you add the boot option "intel_idle.max_cstate=0" it should cause the system to use the acpi idle driver instead of the Intel idle driver.&lt;/P&gt;

&lt;P&gt;It is not surprising that the two idle drivers show different states -- the Intel idle driver probably understands the hardware better than the ACPI idle driver.&lt;/P&gt;

&lt;P&gt;You might want to try the same tests without the special boot option and see if the system still obeys the /dev/cpu_dma_latency control.&amp;nbsp;&amp;nbsp; If it works, then the whole process becomes much easier!&lt;/P&gt;</description>
      <pubDate>Tue, 23 Jun 2015 19:54:56 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Tuning-Performance/Disable-C6-C7-C-state-for-core/m-p/1045852#M4684</guid>
      <dc:creator>McCalpinJohn</dc:creator>
      <dc:date>2015-06-23T19:54:56Z</dc:date>
    </item>
    <item>
      <title>So I tried writing latency</title>
      <link>https://community.intel.com/t5/Software-Tuning-Performance/Disable-C6-C7-C-state-for-core/m-p/1045853#M4685</link>
      <description>&lt;P&gt;So I tried writing latency values to cpu_dma_latency file without the special boot option and it works fine. So I guess, it is not needed, at least for my machine! Thanks for your help.&lt;/P&gt;</description>
      <pubDate>Wed, 24 Jun 2015 14:50:59 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Tuning-Performance/Disable-C6-C7-C-state-for-core/m-p/1045853#M4685</guid>
      <dc:creator>BGoel</dc:creator>
      <dc:date>2015-06-24T14:50:59Z</dc:date>
    </item>
    <item>
      <title>So I found that I can control</title>
      <link>https://community.intel.com/t5/Software-Tuning-Performance/Disable-C6-C7-C-state-for-core/m-p/1045854#M4686</link>
      <description>&lt;P&gt;So I found that I can control the c-state individually for each core by just writing '0' or '1' to file&amp;nbsp;/sys/devices/system/cpu/cpu[0123]/cpuidle/state[012345]/disable. I am wondering if there are any downsides to controlling c-states this way!&lt;/P&gt;</description>
      <pubDate>Wed, 24 Jun 2015 17:59:00 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Tuning-Performance/Disable-C6-C7-C-state-for-core/m-p/1045854#M4686</guid>
      <dc:creator>BGoel</dc:creator>
      <dc:date>2015-06-24T17:59:00Z</dc:date>
    </item>
  </channel>
</rss>

