<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Counting native events in Software Tuning, Performance Optimization &amp; Platform Monitoring</title>
    <link>https://community.intel.com/t5/Software-Tuning-Performance/Counting-native-events/m-p/1056369#M4989</link>
    <description>&lt;P&gt;Hi,&lt;/P&gt;

&lt;P&gt;I try to count some performance events of a part of an application written in C.&lt;/P&gt;

&lt;P&gt;So far, I have used PAPI to count events. It works fine for preset events. However, when I profile native events, all of them turn out to be translated into the same Event Code :&amp;nbsp;0x40000022 (an output of papi_avail is below). It makes no sense, but no error occurs when I profile them. What could be wrong ? How could I debug this ?&lt;/P&gt;

&lt;P&gt;Also, I've got a list (from the perfmon directory) of events that can be counted for the architecture I work with (Ivy bridge) and the adresses and values of the associated registers. Is there an alternative to PAPI I could use to count a particular event of that list, over a certain part of the program, knowing the name of the event and the registers informations ?&amp;nbsp;&lt;SPAN style="font-size: 1em; line-height: 1.5;"&gt;Would it work to simply write and read to the corresponding registers manually (for example using pcm-msr) ?&lt;/SPAN&gt;&lt;/P&gt;

&lt;P&gt;&lt;SPAN style="font-size: 1em; line-height: 1.5;"&gt;Thanks in advance for your help,&lt;/SPAN&gt;&lt;/P&gt;

&lt;P&gt;Vincent&lt;/P&gt;

&lt;P class="p1"&gt;&amp;nbsp;&lt;/P&gt;

&lt;P class="p1"&gt;&lt;SPAN class="s1"&gt;$ &lt;/SPAN&gt;papi_avail -e LLC_MISSES&lt;/P&gt;

&lt;P class="p1"&gt;Available events and hardware information.&lt;/P&gt;

&lt;P class="p1"&gt;--------------------------------------------------------------------------------&lt;/P&gt;

&lt;P class="p1"&gt;PAPI Version &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; : 5.3.0.0&lt;/P&gt;

&lt;P class="p1"&gt;Vendor string and code &amp;nbsp; : GenuineIntel (1)&lt;/P&gt;

&lt;P class="p1"&gt;Model string and code&amp;nbsp; &amp;nbsp; : Intel(R) Xeon(R) CPU E5-4610 v2 @ 2.30GHz (62)&lt;/P&gt;

&lt;P class="p1"&gt;CPU Revision &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; : 4.000000&lt;/P&gt;

&lt;P class="p1"&gt;CPUID Info &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; : Family: 6&amp;nbsp; Model: 62&amp;nbsp; Stepping: 4&lt;/P&gt;

&lt;P class="p1"&gt;CPU Max Megahertz&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; : 2294&lt;/P&gt;

&lt;P class="p1"&gt;CPU Min Megahertz&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; : 2294&lt;/P&gt;

&lt;P class="p1"&gt;Hdw Threads per core &amp;nbsp; &amp;nbsp; : 1&lt;/P&gt;

&lt;P class="p1"&gt;Cores per Socket &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; : 8&lt;/P&gt;

&lt;P class="p1"&gt;Sockets&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; : 4&lt;/P&gt;

&lt;P class="p1"&gt;NUMA Nodes &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; : 4&lt;/P&gt;

&lt;P class="p1"&gt;CPUs per Node&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; : 8&lt;/P&gt;

&lt;P class="p1"&gt;Total CPUs &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; : 32&lt;/P&gt;

&lt;P class="p1"&gt;Running in a VM&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; : no&lt;/P&gt;

&lt;P class="p1"&gt;Number Hardware Counters : 11&lt;/P&gt;

&lt;P class="p1"&gt;Max Multiplex Counters &amp;nbsp; : 64&lt;/P&gt;

&lt;P class="p1"&gt;--------------------------------------------------------------------------------&lt;/P&gt;

&lt;P class="p2"&gt;&amp;nbsp;&lt;/P&gt;

&lt;P class="p1"&gt;Event name: &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; LLC_MISSES&lt;/P&gt;

&lt;P class="p1"&gt;Event Code: &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; 0x40000022 &amp;nbsp;&lt;/P&gt;

&lt;P class="p1"&gt;Number of Register Values:&amp;nbsp; &amp;nbsp; 0&lt;/P&gt;

&lt;P class="p1"&gt;Description: &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; |Alias for LAST_LEVEL_CACHE_MISSES|&lt;/P&gt;

&lt;P class="p2"&gt;&amp;nbsp;&lt;/P&gt;

&lt;P class="p1"&gt;Unit Masks:&lt;/P&gt;

&lt;P class="p1"&gt;&amp;nbsp;Mask Info:&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; |:e=0|edge level (may require counter-mask &amp;gt;= 1)|&lt;/P&gt;

&lt;P class="p1"&gt;&amp;nbsp;Mask Info:&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; |:i=0|invert|&lt;/P&gt;

&lt;P class="p1"&gt;&amp;nbsp;Mask Info:&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; |:c=0|counter-mask in range [0-255]|&lt;/P&gt;

&lt;P class="p1"&gt;&amp;nbsp;Mask Info:&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; |:t=0|measure any thread|&lt;/P&gt;

&lt;P class="p1"&gt;&amp;nbsp;Mask Info:&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; |:u=0|monitor at user level|&lt;/P&gt;

&lt;P class="p1"&gt;&amp;nbsp;Mask Info:&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; |:k=0|monitor at kernel level|&lt;/P&gt;

&lt;P class="p1"&gt;-------------------------------------------------------------------------&lt;/P&gt;

&lt;P class="p1"&gt;avail.c &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; PASSED&lt;/P&gt;</description>
    <pubDate>Mon, 29 Jun 2015 15:08:33 GMT</pubDate>
    <dc:creator>Vincent_B_1</dc:creator>
    <dc:date>2015-06-29T15:08:33Z</dc:date>
    <item>
      <title>Counting native events</title>
      <link>https://community.intel.com/t5/Software-Tuning-Performance/Counting-native-events/m-p/1056369#M4989</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;

&lt;P&gt;I try to count some performance events of a part of an application written in C.&lt;/P&gt;

&lt;P&gt;So far, I have used PAPI to count events. It works fine for preset events. However, when I profile native events, all of them turn out to be translated into the same Event Code :&amp;nbsp;0x40000022 (an output of papi_avail is below). It makes no sense, but no error occurs when I profile them. What could be wrong ? How could I debug this ?&lt;/P&gt;

&lt;P&gt;Also, I've got a list (from the perfmon directory) of events that can be counted for the architecture I work with (Ivy bridge) and the adresses and values of the associated registers. Is there an alternative to PAPI I could use to count a particular event of that list, over a certain part of the program, knowing the name of the event and the registers informations ?&amp;nbsp;&lt;SPAN style="font-size: 1em; line-height: 1.5;"&gt;Would it work to simply write and read to the corresponding registers manually (for example using pcm-msr) ?&lt;/SPAN&gt;&lt;/P&gt;

&lt;P&gt;&lt;SPAN style="font-size: 1em; line-height: 1.5;"&gt;Thanks in advance for your help,&lt;/SPAN&gt;&lt;/P&gt;

&lt;P&gt;Vincent&lt;/P&gt;

&lt;P class="p1"&gt;&amp;nbsp;&lt;/P&gt;

&lt;P class="p1"&gt;&lt;SPAN class="s1"&gt;$ &lt;/SPAN&gt;papi_avail -e LLC_MISSES&lt;/P&gt;

&lt;P class="p1"&gt;Available events and hardware information.&lt;/P&gt;

&lt;P class="p1"&gt;--------------------------------------------------------------------------------&lt;/P&gt;

&lt;P class="p1"&gt;PAPI Version &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; : 5.3.0.0&lt;/P&gt;

&lt;P class="p1"&gt;Vendor string and code &amp;nbsp; : GenuineIntel (1)&lt;/P&gt;

&lt;P class="p1"&gt;Model string and code&amp;nbsp; &amp;nbsp; : Intel(R) Xeon(R) CPU E5-4610 v2 @ 2.30GHz (62)&lt;/P&gt;

&lt;P class="p1"&gt;CPU Revision &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; : 4.000000&lt;/P&gt;

&lt;P class="p1"&gt;CPUID Info &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; : Family: 6&amp;nbsp; Model: 62&amp;nbsp; Stepping: 4&lt;/P&gt;

&lt;P class="p1"&gt;CPU Max Megahertz&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; : 2294&lt;/P&gt;

&lt;P class="p1"&gt;CPU Min Megahertz&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; : 2294&lt;/P&gt;

&lt;P class="p1"&gt;Hdw Threads per core &amp;nbsp; &amp;nbsp; : 1&lt;/P&gt;

&lt;P class="p1"&gt;Cores per Socket &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; : 8&lt;/P&gt;

&lt;P class="p1"&gt;Sockets&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; : 4&lt;/P&gt;

&lt;P class="p1"&gt;NUMA Nodes &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; : 4&lt;/P&gt;

&lt;P class="p1"&gt;CPUs per Node&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; : 8&lt;/P&gt;

&lt;P class="p1"&gt;Total CPUs &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; : 32&lt;/P&gt;

&lt;P class="p1"&gt;Running in a VM&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; : no&lt;/P&gt;

&lt;P class="p1"&gt;Number Hardware Counters : 11&lt;/P&gt;

&lt;P class="p1"&gt;Max Multiplex Counters &amp;nbsp; : 64&lt;/P&gt;

&lt;P class="p1"&gt;--------------------------------------------------------------------------------&lt;/P&gt;

&lt;P class="p2"&gt;&amp;nbsp;&lt;/P&gt;

&lt;P class="p1"&gt;Event name: &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; LLC_MISSES&lt;/P&gt;

&lt;P class="p1"&gt;Event Code: &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; 0x40000022 &amp;nbsp;&lt;/P&gt;

&lt;P class="p1"&gt;Number of Register Values:&amp;nbsp; &amp;nbsp; 0&lt;/P&gt;

&lt;P class="p1"&gt;Description: &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; |Alias for LAST_LEVEL_CACHE_MISSES|&lt;/P&gt;

&lt;P class="p2"&gt;&amp;nbsp;&lt;/P&gt;

&lt;P class="p1"&gt;Unit Masks:&lt;/P&gt;

&lt;P class="p1"&gt;&amp;nbsp;Mask Info:&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; |:e=0|edge level (may require counter-mask &amp;gt;= 1)|&lt;/P&gt;

&lt;P class="p1"&gt;&amp;nbsp;Mask Info:&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; |:i=0|invert|&lt;/P&gt;

&lt;P class="p1"&gt;&amp;nbsp;Mask Info:&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; |:c=0|counter-mask in range [0-255]|&lt;/P&gt;

&lt;P class="p1"&gt;&amp;nbsp;Mask Info:&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; |:t=0|measure any thread|&lt;/P&gt;

&lt;P class="p1"&gt;&amp;nbsp;Mask Info:&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; |:u=0|monitor at user level|&lt;/P&gt;

&lt;P class="p1"&gt;&amp;nbsp;Mask Info:&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; |:k=0|monitor at kernel level|&lt;/P&gt;

&lt;P class="p1"&gt;-------------------------------------------------------------------------&lt;/P&gt;

&lt;P class="p1"&gt;avail.c &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; PASSED&lt;/P&gt;</description>
      <pubDate>Mon, 29 Jun 2015 15:08:33 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Tuning-Performance/Counting-native-events/m-p/1056369#M4989</guid>
      <dc:creator>Vincent_B_1</dc:creator>
      <dc:date>2015-06-29T15:08:33Z</dc:date>
    </item>
    <item>
      <title>Vincent,</title>
      <link>https://community.intel.com/t5/Software-Tuning-Performance/Counting-native-events/m-p/1056370#M4990</link>
      <description>&lt;P&gt;Vincent,&lt;/P&gt;

&lt;P&gt;&lt;SPAN style="font-size: 1em; line-height: 1.5;"&gt;Unfortunately, I'm can't help you with PAPI but you might want to have a look at &lt;/SPAN&gt;&lt;A href="https://software.intel.com/en-us/articles/intel-performance-counter-monitor" style="font-size: 1em; line-height: 1.5;"&gt;Intel Performance Counter Monitor&lt;/A&gt;&lt;SPAN style="font-size: 1em; line-height: 1.5;"&gt;. It can be used to count L3 misses on some systems.&lt;/SPAN&gt;&lt;/P&gt;

&lt;P&gt;&amp;nbsp;&lt;/P&gt;

&lt;P&gt;Kind regards&lt;/P&gt;

&lt;P&gt;Thomas&lt;/P&gt;</description>
      <pubDate>Mon, 29 Jun 2015 15:38:37 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Tuning-Performance/Counting-native-events/m-p/1056370#M4990</guid>
      <dc:creator>Thomas_W_Intel</dc:creator>
      <dc:date>2015-06-29T15:38:37Z</dc:date>
    </item>
  </channel>
</rss>

