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    <title>topic Intel Hyper Threading in Software Tuning, Performance Optimization &amp; Platform Monitoring</title>
    <link>https://community.intel.com/t5/Software-Tuning-Performance/Intel-Hyper-Threading/m-p/1057335#M5017</link>
    <description>&lt;P&gt;Hello,&lt;/P&gt;

&lt;P&gt;Our OS: Linux 6.4 Santiago with 32 Core Servers and HT Enabled.&lt;/P&gt;

&lt;P&gt;We are a financial trading software firm and during the performance optimization we observed&amp;nbsp;&lt;/P&gt;

&lt;P&gt;L1D Replacement % = 1.0&lt;/P&gt;

&lt;P&gt;&lt;SPAN style="font-size: 13.0080003738403px; line-height: 19.5120010375977px;"&gt;L2D Replacement % = 1.0&lt;/SPAN&gt;&lt;/P&gt;

&lt;P&gt;&lt;SPAN style="font-size: 13.0080003738403px; line-height: 19.5120010375977px;"&gt;LLC Replacement % = 1.0&lt;/SPAN&gt;&lt;/P&gt;

&lt;P&gt;&lt;SPAN style="font-size: 13.0080003738403px; line-height: 19.5120010375977px;"&gt;in our VTune output.&lt;/SPAN&gt;&lt;/P&gt;

&lt;P&gt;&lt;SPAN style="font-size: 13.0080003738403px; line-height: 19.5120010375977px;"&gt;Our application is completely single threaded and we are making sure that the make application thread is always pinned to a core. Is it a possibility that because of HT enabled we see the above numbers because cores on the same processor share resources like L1D, DTLB, ITLB? Has anyone seen this kind of behavior before.&lt;/SPAN&gt;&lt;/P&gt;

&lt;P&gt;&lt;SPAN style="font-size: 13.0080003738403px; line-height: 19.5120010375977px;"&gt;For trading applications where latency matters does switching HT off is advisable?&lt;/SPAN&gt;&lt;/P&gt;

&lt;P&gt;Thanks.&lt;/P&gt;</description>
    <pubDate>Thu, 20 Aug 2015 03:49:23 GMT</pubDate>
    <dc:creator>Amit_T_1</dc:creator>
    <dc:date>2015-08-20T03:49:23Z</dc:date>
    <item>
      <title>Intel Hyper Threading</title>
      <link>https://community.intel.com/t5/Software-Tuning-Performance/Intel-Hyper-Threading/m-p/1057335#M5017</link>
      <description>&lt;P&gt;Hello,&lt;/P&gt;

&lt;P&gt;Our OS: Linux 6.4 Santiago with 32 Core Servers and HT Enabled.&lt;/P&gt;

&lt;P&gt;We are a financial trading software firm and during the performance optimization we observed&amp;nbsp;&lt;/P&gt;

&lt;P&gt;L1D Replacement % = 1.0&lt;/P&gt;

&lt;P&gt;&lt;SPAN style="font-size: 13.0080003738403px; line-height: 19.5120010375977px;"&gt;L2D Replacement % = 1.0&lt;/SPAN&gt;&lt;/P&gt;

&lt;P&gt;&lt;SPAN style="font-size: 13.0080003738403px; line-height: 19.5120010375977px;"&gt;LLC Replacement % = 1.0&lt;/SPAN&gt;&lt;/P&gt;

&lt;P&gt;&lt;SPAN style="font-size: 13.0080003738403px; line-height: 19.5120010375977px;"&gt;in our VTune output.&lt;/SPAN&gt;&lt;/P&gt;

&lt;P&gt;&lt;SPAN style="font-size: 13.0080003738403px; line-height: 19.5120010375977px;"&gt;Our application is completely single threaded and we are making sure that the make application thread is always pinned to a core. Is it a possibility that because of HT enabled we see the above numbers because cores on the same processor share resources like L1D, DTLB, ITLB? Has anyone seen this kind of behavior before.&lt;/SPAN&gt;&lt;/P&gt;

&lt;P&gt;&lt;SPAN style="font-size: 13.0080003738403px; line-height: 19.5120010375977px;"&gt;For trading applications where latency matters does switching HT off is advisable?&lt;/SPAN&gt;&lt;/P&gt;

&lt;P&gt;Thanks.&lt;/P&gt;</description>
      <pubDate>Thu, 20 Aug 2015 03:49:23 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Tuning-Performance/Intel-Hyper-Threading/m-p/1057335#M5017</guid>
      <dc:creator>Amit_T_1</dc:creator>
      <dc:date>2015-08-20T03:49:23Z</dc:date>
    </item>
    <item>
      <title>On the question of how</title>
      <link>https://community.intel.com/t5/Software-Tuning-Performance/Intel-Hyper-Threading/m-p/1057336#M5018</link>
      <description>&lt;P&gt;On the question of how HyperThreading affects partition of core resources, you might check the Intel Architecture manuals for information on the CPU family of interest to you.&lt;/P&gt;

&lt;P&gt;Several of the important resources are shared dynamically between the pair of logical processors, so that a single thread can utilize all of them, provided that no other thread interrupts their use on that core.&amp;nbsp; When I last studied the matter, ITLB was an exception, where a thread could use only half the entries for that core, even when HT is disabled.&amp;nbsp; It was said that architects believed that most applications which would run best with HT disabled did not need the additional ITLB, due to (assumed) higher instruction locality than those for which HT was designed.&lt;/P&gt;

&lt;P&gt;Documents on such matters for new CPUs tend to remain under non-disclosure for a while after the CPU is released to market.&lt;/P&gt;

&lt;P&gt;It's probably possible to run specific tests to see how much of the resource a thread can use.&lt;/P&gt;</description>
      <pubDate>Thu, 20 Aug 2015 05:55:00 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Tuning-Performance/Intel-Hyper-Threading/m-p/1057336#M5018</guid>
      <dc:creator>TimP</dc:creator>
      <dc:date>2015-08-20T05:55:00Z</dc:date>
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