https://community.intel.com/t5/Software-Tuning-Performance/DMA-synchronisation-with-incoming-MWr-TLP/m-p/1063674#M5189 <P>Hello Intel-Forum,</P> <P>The hardware is a i7-4770S with a board plugged into the x16 PCIe slot. The board is sending a Memory-Write TLP over the PCIe bus to the root complex. This root complex is the i7 die. The only documentation I could find about the further processing of the TLP is the Core2-documentation.</P> <P>By this documentation I very much assume that one of the next stations for the data is the DMA control unit. Is this assumption right?</P> <P>This unit will deal with the data and make it available for CPU-directives. I still have to figure out on which address the data will be available, but this can be OS specific. As far as I have heard will be the address in the TLP an offset to a dedicated memory.(Thanks in advance for any hint on this...)</P> <P>Is it possible to subscribe to a synchronisation trigger from the DMA unit, e.g. an interrupt, to wake up when the data are accessible?</P> <P>&nbsp;</P> <P>regards</P> <P>AppleCake</P> <P>&nbsp;</P> Mon, 08 Feb 2016 14:55:43 GMT Pay_S_ 2016-02-08T14:55:43Z https://community.intel.com/t5/Software-Tuning-Performance/DMA-synchronisation-with-incoming-MWr-TLP/m-p/1063674#M5189 <P>Hello Intel-Forum,</P> <P>The hardware is a i7-4770S with a board plugged into the x16 PCIe slot. The board is sending a Memory-Write TLP over the PCIe bus to the root complex. This root complex is the i7 die. The only documentation I could find about the further processing of the TLP is the Core2-documentation.</P> <P>By this documentation I very much assume that one of the next stations for the data is the DMA control unit. Is this assumption right?</P> <P>This unit will deal with the data and make it available for CPU-directives. I still have to figure out on which address the data will be available, but this can be OS specific. As far as I have heard will be the address in the TLP an offset to a dedicated memory.(Thanks in advance for any hint on this...)</P> <P>Is it possible to subscribe to a synchronisation trigger from the DMA unit, e.g. an interrupt, to wake up when the data are accessible?</P> <P>&nbsp;</P> <P>regards</P> <P>AppleCake</P> <P>&nbsp;</P> Mon, 08 Feb 2016 14:55:43 GMT https://community.intel.com/t5/Software-Tuning-Performance/DMA-synchronisation-with-incoming-MWr-TLP/m-p/1063674#M5189 Pay_S_ 2016-02-08T14:55:43Z