https://community.intel.com/t5/Software-Tuning-Performance/Enabling-LBR-fails-quitely/m-p/1068486#M5267 <P>Hey,</P> <P>My code enables LBR by setting 0x1 to DEBUG_CTL MSR (0x1d9), and works properly on 1 PC and 1 Server i've checked so far.</P> <P>I'm executing the same code on XEON E5-2620, but when i read the MSR after setting, it's still 0, and the LBR stack is empty... is there anything special i need to do to set the LBR flag for this kind of processor? (don't know if it matters, but it is a multi processor server).</P> <P>Thanks.</P> Fri, 20 May 2016 09:29:29 GMT Maor_H_ 2016-05-20T09:29:29Z https://community.intel.com/t5/Software-Tuning-Performance/Enabling-LBR-fails-quitely/m-p/1068486#M5267 <P>Hey,</P> <P>My code enables LBR by setting 0x1 to DEBUG_CTL MSR (0x1d9), and works properly on 1 PC and 1 Server i've checked so far.</P> <P>I'm executing the same code on XEON E5-2620, but when i read the MSR after setting, it's still 0, and the LBR stack is empty... is there anything special i need to do to set the LBR flag for this kind of processor? (don't know if it matters, but it is a multi processor server).</P> <P>Thanks.</P> Fri, 20 May 2016 09:29:29 GMT https://community.intel.com/t5/Software-Tuning-Performance/Enabling-LBR-fails-quitely/m-p/1068486#M5267 Maor_H_ 2016-05-20T09:29:29Z