topic Over-writing an instruction in Software Tuning, Performance Optimization & Platform Monitoring

Disabling instruction cache

JLie — Sat, 16 Jan 2016 11:19:14 GMT

Hello,

I need to test some code without the cpu caching the next instructions or reading them from its cache. For all the x86_64 family.

Is there a mode which prevents the cpu from reading instructions from cache? it will *massively* impact the performance of the app, but at this stage (before the release), it doesn't matter. I guess setting the memory to "direct" instead of "write back" should help, but not sure it that would be enough.

The why of all this is very specific and only for development stage (who would run a late cpu with crappy performance). I don't need an alternative solution but this one.

Thanks

Over-writing an instruction

TimP — Sat, 16 Jan 2016 11:43:03 GMT

Over-writing an instruction in a cache line will invalidate the cached line. Perhaps that's even more of a delay than you want.

Thanks Tim,

JLie — Sat, 16 Jan 2016 11:46:45 GMT

Thanks Tim,

Is that always the case? I mean isn't there a corner case that would crush my strategy?

The processor is certainly

McCalpinJohn — Tue, 19 Jan 2016 18:19:23 GMT

The processor is certainly capable of operating with the cache(s) disabled, as described in Chapter 11 (especially section 11.5) of Volume 3 of the Intel Architecture SW Developer's Manual (document 325384). I would not be so certain that your operating system would work under these circumstances -- the cache-disabled modes are typically only used during the boot process.

It is certainly possible (under Linux, anyway) to write a device driver that reserves a portion of system memory and marks it as uncacheable. It is pretty easy to use this for data -- the device drive provides an MMIO function that returns a user-space pointer to the beginning of this address range. I have never seen instructions on how to set up the "text" of an executable to be mapped to a particular physical address range, but it seems likely that this could be hacked.

I don't know if you are guaranteed that Intel processors will not cache instructions in the decoded uop cache when the instruction addresses are to UC memory. Most of the discussion in the architecture manuals is about data accesses in uncached space, and I have not seen much discussion about instruction fetches from uncached space.